DM336P Davicom Semiconductor Incorporated, DM336P Datasheet - Page 15
DM336P
Manufacturer Part Number
DM336P
Description
Manufacturer
Davicom Semiconductor Incorporated
Datasheet
1.DM336P.pdf
(40 pages)
(1) Card Control Registers (continued)
(2) Logical Device Control Registers
c. Logical Device Configuration Registers
(1) I/O Configuration Registers
(2) Interrupt Configuration Registers
(3) Vender Define Register
Final
Version: DM336P-DS-F02
August 15, 2000
Index
Index
Index
Index
Index
F0H
F1H
F2H
07H
30H
31H
60H
61H
70H
71H
IRQ type bits [7:0]
Auto Configuration
IRQ Status Enable
I/O Range Check
I/O base address
I/O base address
Logical Device
IRQ level
IRQ Status
Name
Activate
bits[15:8]
Name
Name
bits[7:3]
Name
Name
Type
R/W
Type
Type
R/W For each logical device, there is one Activate register that controls
R/W This register is used to perform a conflict check on the I/O port range
R
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Type
R/W
R
Type
R/W Read/write value indicating the selected I/O Lower Limit Address Bits
R/W Read/write value indicating the selected I/O Lower Input Address Bits
W
R
00H (Only one logical device in DM6383A)
whether or not the device is active on the ISA bus. Bit[0], if set, activates
the logical device. Before a logical device is activated, I/O range check
must be disabled.
programmed for use by a logical device.
Bit[1] - This bit, when set, enables I/O range check. I/O port range check
is only valid when the logical device is inactive.
Bit[0] - If set, this bit forces logical device to respond to I/O reads within
logical device assigned I/O range with a 55H when I/O range check is in
operation. If clear, the logical device drives AAH.
Read/write value indicating a selected Interrupt Level Bits[3:0] Select
which ISA interrupt level is used. A value of 1 selects IRQ1, 15 selects
IRQ15, etc. IRQ0 is not a valid interrupt selection.
Read/write value indicating which type of interrupt is used for the IRQ
selected above Bit[1] - Level, 1 = high, 0 = low Bit[0] - Type, 1= level, 0 =
edge for DM6383A, this register is read only with value = 02H.
[15:8] for I/O descriptor 0. If a logical device indicates it uses only 10
bits for decoding, then bits [15:10] need not to be supported.
[7:3] for I/O descriptor 0.
The I/O base address and IRQ can be configured by CPU through this
register. (It can also be configured by micro-controller. See previous
section).
Before reading IRQ lines status, bit 0 must be set in order to load IRQ
lines status to IRQ Status register, bit 1 enable Pull Low resistor.
This register responds to IRQ lines status to determine which interrupt
has been used by PC system. bit 0: IRQ 3 bit 1: IRQ 4 bit 2: IRQ 5 bit 3:
IRQ 7 bit 4: IRQ 10 bit 5: IRQ11 bit 6: IRQ12 bit 7: IRQ15.
Definition
Definition
Definition
Definition
Definition
DM336P
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