AT94KAL ATMEL Corporation, AT94KAL Datasheet - Page 4

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AT94KAL

Manufacturer Part Number
AT94KAL
Description
5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
Manufacturer
ATMEL Corporation
Datasheet
4
AT94KAL Series FPSLIC Summary
The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing
powerful instructions in a single-clock cycle, and allows system designers to optimize power
consumption versus processing speed. The AVR core is based on an enhanced RISC architec-
ture that combines a rich instruction set with 32 general-purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code-efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on-chip
SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be auto-
matically loaded at system power-up using Atmel’s In-System Programmable (ISP) AT17 Series
EEPROM Configuration Memories.
State-of-the-art FPSLIC design tools, System Designer, were developed in conjunction with the
FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller devel-
opment and debug, FPGA development and Place and Route, and complete system
co-verification in one easy-to-use software tool.
Table 1-2.
FPSLIC Device
AT94K05
AT94K10
AT94K40
FPSLIC Configuration Devices
FPSLIC Configuration
AT17LV256
AT17LV512
AT17LV010
Device
Configuration Data
226520 Bits
430488 Bits
815382 Bits
Spare Memory
233194 Bits
35624 Bits
93800 Bits
1138IS–FPSLI–1/08

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