AT94S_05 ATMEL Corporation, AT94S_05 Datasheet - Page 17
AT94S_05
Manufacturer Part Number
AT94S_05
Description
Secure 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage Eeprom
Manufacturer
ATMEL Corporation
Datasheet
1.AT94S_05.pdf
(32 pages)
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4.15
5. Packaging and Pin List information
2314E–FPSLI–6/05
Chip Erase Timing
The entire device can be erased at once by writing to a specific address. This operation will
erase the entire array. See
Table 4-2.
Figure 4-5.
Table 5-1.
Table 5-2.
Symbol
Tec
Part #
BG256
LQ144
Pin
TDI
TDO
TMS
TCK
SDA
SCL
Chip Erase Cycle Characteristics
Chip Erase Timing Diagram
Part and Package Combinations Available
AT94K JTAG ICE Pin List
tsu.dat
8th BIT
Parameter
Chip Erase Cycle Time (25 ms)
Package
96 FPGA I/O
DG
BQ
Table 4-2
AT94S05
IO34
IO38
IO43
IO44
ACK
tnd.dat
thigh
for specifics on the write algorithm.
tlow
AT94S05
Condition
STOP
93
–
192 FPGA I/O
AT94S10
AT94S Secure Family
IO50
IO54
IO63
IO64
AT94S10
Tec
137
84
384 FPGA I/O
AT94S40
IO102
IO123
IO124
IO98
Condition
AT94S40
START
162
84
17
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