AT91M42800A ATMEL Corporation, AT91M42800A Datasheet - Page 4

• Manufacturer Part Number: AT91M42800A
• Description: The AT91M42800A Features 8K Bytes of On-chip SRAM, an External Bus Interface, a 6-channel Timer/Counter, 2 Usarts, 2 Master/slave Spi Interfaces, 3 System Timers And an Advanced Power Management Controller.
• Manufacturer: ATMEL Corporation

8. Possible Glitches on MCKO while Commuting Clock
7. Initializing SPI in Master Mode May Cause Problems
6. Break is Sent before Last Written Character
5. End of Break is not Guaranteed
4. SCK is Ignored at 32 kHz
3. SCK Maximum Frequency Relative to MCK in Synchronous Mode
2. PIO Input Filters are not Bit-to-bit Selectable
4
Unpredictable transitional pulses may occur on the MCKO pin when modifying the MCKOSS field in the PMC Clock
Generator Mode Register. The length of these glitches can be lower than the lowest period of the selected or current
clock. When switching from the Slow Clock (i.e., after reset) to any of the PLL outputs (inverted or divided by 2), a pulse
of less than 10 ns is output on the pin MCKO.
Problem Fix/Workaround
The glitch description above is merely a user warning/possibility. If the glitches do occur, there is no Problem
Fix/Workaround to propose.
Initializing the SPI in master mode may cause a mode fault detection.
Problem Fix/Workaround
In or der to prev ent this error , the user should pull up the PA14/NPCSA0/NSSA pin for SPIA or the
PA21/NPCSA0/NSSB pin for SPIB to the V
When the Start Break command is activated in the USART Control Register and while a character is in the USART
Transmit Holding Register, the break is transmitted before the character.
Problem Fix/Workaround
The user must wait for the TXEMPTY flag in the USART Status Register before sending a break command.
When performing a Stop Break command, the USART transmitter normally inserts a “12-bit at level 1” sequence after
the break. This feature is not guaranteed.
Problem Fix/Workaround
The user must use the Time Guard programmed at the value 12.
If the origin of the Master Clock is the Slow Clock, the USART Channels cannot be synchronized with a clock that
comes from the SCK pin.
Problem Fix/Workaround
No problem fix/workaround to propose.
In USART Synchronous Mode, the external clock frequency (SCK) must be at least 10 times lower than the Master
Clock.
Problem Fix/Workaround
No problem fix/workaround to propose.
The PIO input filters are enabled and disabled only for all of the PIO input pins and not individually. To activate them,
the user must write 0x0001 in the PIO IFER and 0x0001 in the PIO IFDR to deactivate them.
Problem Fix/Workaround
No problem fix/workaround to propose.
AT91M42800A Errata Sheet
DDIO
power supply.
1782B–01/02