AT91FR4042 ATMEL Corporation, AT91FR4042 Datasheet - Page 12

• Manufacturer Part Number: AT91FR4042
• Description: The AT91FR4042 Features 256K Bytes of On-chip SRAM, 512K Bytes of Flash, an External Bus Interface, a 3-channel Timer/Counter, 2 Usarts, a Watchdog Timer And Advanced Power-saving Features.
• Manufacturer: ATMEL Corporation

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AT91FR4042
Preliminary
During boot, the EBI must be configured with correct number of standard wait states. As
an example, five standard wait states are required when the microcontroller is running at
66 MHz.
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to
their respective supplies by the shortest route. The Flash memory powers-on in read
mode. Command sequences are used to place the device in other operating modes,
such as program and erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high
level, the memory is in its standard operating mode; a low level on this input halts the
current memory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a
program cycle is in progress, an attempted read of the last word written will return the
complement of the written data on I/O7. An open-drain NBUSY output pin provides
another method of detecting the end of a program or erase cycle. This pin is pulled low
while program and erase cycles are in progress and is released at the completion of the
cycle. A toggle bit feature provides a third means of detecting the end of a program or
erase cycle.
The Flash memory is divided into 4 sectors for erase operations.
The device has the capability to protect data stored in the 8K words boot block sector.
Once the data protection for this sector is enabled, the data in the sector cannot be
changed while input levels lie between ground and VDDIO. The address range of the
boot block is 00000h to 01FFFh
The user can override the boot block programing lockout by applying a 12V input signal
to the RESET pin while performing a chip erase, sector erase or word programing
operation.
A 4-byte command sequence (Enter Single Pulse Program Mode) allows the device to
be written to directly, using single pulses on the write control lines. This mode (Single-
pulse Programming) is exited by powering down the device or by pulsing the NRSTF pin
low for a minimum of 50 ns and then bringing it back to VDDIO.
The following hardware features protect against inadvertent programming of the Flash
memory:
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See the AT49BV4096A 4-megabit (256K x 16/512K x 8) Single 2.7 volt Flash Memory
Datasheet for further details on Flash operation and electrical characteristics.
VDDIO Sense – if VDDIO is below 1.8V (typical), the program function is inhibited.
VDDIO Power-on Delay – once VDDIO has reached the VDDIO sense level, the
device will automatically time out 10 ms (typically) before programming.
Program Inhibit – holding any one of OE low, CE high or WE high inhibits program
cycles.
Noise Filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not
initiate a program cycle.
2648B–ATARM–12/02