MAX5893 Maxim Integrated Products, MAX5893 Datasheet - Page 29

• Manufacturer Part Number: MAX5893
• Description: 12-Bit/ 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
• Manufacturer: Maxim Integrated Products

Grounding and power-supply decoupling strongly influ-
ence the MAX5893 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro-
magnetic interference (EMI) can either couple into or
be generated by the MAX5893. Observe the grounding
and power-supply decoupling guidelines for high-
speed, high-frequency applications. Follow the power-
supply and filter configuration guidelines to achieve
optimum dynamic performance.
Using a multilayer PCB with separate ground and
power-supply planes, run high-speed signals on lines
directly above the ground plane. Since the MAX5893
has separate analog and digital sections, the PCB
should include separate analog and digital ground sec-
tions with only one point connecting the three planes at
the exposed pad under the MAX5893. Run digital sig-
nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Keep
digital signals as far away from sensitive analog inputs,
reference lines, and clock inputs as practical. Use a
symmetric design of clock input and the analog output
lines to minimize 2nd-order harmonic distortion compo-
nents, thus optimizing the dynamic performance of the
DAC. Keep digital signal paths short and run lengths
matched to avoid propagation delay and data skew
mismatches.
The MAX5893 requires five separate power-supply
inputs for the analog (AV
(DV
Decouple each voltage supply pin with a separate
0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-net-
work could also improve performance.
The exposed pad (EP) MUST be soldered to the
ground. Use multiple vias, an array of at least 4 x 4
vias, directly under the EP to provide a low thermal and
electrical impedance path for the IC.
DD1.8
12-Bit, 500Msps Interpolating and Modulating
and DV
DD3.3
______________________________________________________________________________________
Power Supplies, Bypassing,
), and clock (AV
Decoupling, and Layout
DD1.8
and AV
DD3.3
CLK
) circuitry.
), digital
Dual DAC with CMOS Inputs
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full-scale of the
DAC. This error affects all codes by the same amount.
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.
The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in 1Hz bandwidth, specified in dBFS/Hz.
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolu-
tion (N bits):
Static Performance Parameter
SNR
Differential Nonlinearity (DNL)
dB
Dynamic Performance
Signal-to-Noise Ratio (SNR)
= 6.02
Parameter Definitions
Integral Nonlinearity (INL)
Noise Spectral Density
dB
x N + 1.76
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Settling Time
Definitions
dB
Offset Error
Gain Error
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