MAX5876 Maxim Integrated Products, MAX5876 Datasheet - Page 12

• Manufacturer Part Number: MAX5876
• Description: Dual DAC with LVDS Inputs
• Manufacturer: Maxim Integrated Products

12-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
The MAX5876’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
Calculate the full-scale output current as follows:
where I
DAC. R
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
and R
Each MAX5876 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ω termination resistor to ground and a
50Ω resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation
or increased output swing. Figure 3 displays a simpli-
fied diagram of the internal output structure of the
MAX5876.
Figure 2. Reference Architecture, Internal Reference
Configuration
12
OUTFS
I
REF
Analog Outputs (OUTIP, OUTIN, OUTQP,
1µF
______________________________________________________________________________________
I
= V
REF
SET
REFIO
for the differential current outputs of the DAC.
I
OUTFS
SET
OUTFS
R
selections.
SET
/ R
SET
(located between FSADJ and DACREF)
REFIO
FSADJ
DACREF
is the full-scale output current of the
10kΩ
=
REFERENCE
+1.2V
32
×
V
R
REFIO
GND
SET
×
CURRENT-SOURCE
ARRAY DAC



1
−
2
1
12
OUTQN)



OUTIN
OUTIP
OUTFS
The MAX5876 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AV
the differential clock inputs from a single-ended or a
differential clock source. For single-ended operation,
drive CLKP with a logic source and bypass CLKN to
GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AV
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is 5kΩ.
Table 1. I
Matrix Based on a Typical +1.200V
Reference Voltage
Figure 3. Simplified Analog Output Structure
CURRENT I
SWITCHES
CURRENT
AV
CLK
DD
FULL-SCALE
) to achieve optimum jitter performance. Drive
10
15
20
2
5
OUTFS
OUTFS
CURRENT
SOURCES
(mA)
Clock Inputs (CLKP, CLKN)
and R
CALCULATED
SET
19.2
7.68
3.84
2.56
1.92
Selection
R
I
SET
OUT
OUTIN OUTIP
(kΩ)
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1% EIA STD
CLK
19.1
3.83
2.55
1.91
7.5
I
/ 2. This
OUT