MAX5842 Maxim, MAX5842 Datasheet - Page 11

• Manufacturer Part Number: MAX5842
• Description: Quad / 12-Bit / Low-Power / 2-Wire / Serial Voltage-Output DAC
• Manufacturer: Maxim

to the selected power-down mode based on the states
of PD0 and PD1 (Table 1). Any combination of the four
DACs can be controlled with a single write sequence.
In read mode (R/W = 1), the MAX5842 writes the con-
tents of the DAC register to the bus. The direction of
data flow reverses following the address acknowledge
by the MAX5842. The device transmits the first byte of
data, waits for the master to acknowledge, then trans-
mits the second byte. Figure 8 shows an example read
data sequence.
The MAX5842 is compatible with existing I
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typ-
ical I
ports the standard I
general call address is ignored. The MAX5842 address
is compatible with the 7-bit I
only. No 10-bit address formats are supported.
When the MAX5842 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
Figure 6. Example Write Command Sequences
2
C application. The communication protocol sup-
Digital Feedthrough Suppression
MSB
MSB
S
S
______________________________________________________________________________________
Quad, 12-Bit, Low-Power, 2-Wire, Serial
A6
A6
2
C 8-bit communications. The
MSB
MSB
D7
A5
A5
X
D6
A4
A4
X
2
C addressing protocol
D5
A3
A3
D
Read Data Format
I
2
D4
A2
A2
C
C Compatibility
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
D3
A1
A1
B
2
C systems.
EXAMPLE WRITE DATA SEQUENCE
D2
A0
A0
A
R/W
R/W
PD1
LSB
LSB
D1
PD0
LSB
LSB
D0
ACK
ACK
ACK
ACK
The MAX5842 2-wire digital interface is I
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces such as
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
impedance. Bypass V
ground as close to the device as possible.
TRANSISTOR COUNT: 17,213
PROCESS: BiCMOS
Figure 7. Extended Command Byte Definition
MSB
MSB
C3
C3
C2
C2
P
P
Voltage-Output DAC
X
C1
C1
Digital Inputs and Interface Logic
C0
C0
X
Applications Information
D11
D11
Power-Supply Bypassing and
D
D10
D10
DD
C
D9
D9
with a 0.1µF capacitor to
Ground Management
Chip Information
B
LSB
LSB
D8
D8
A
ACK
ACK
PD1
PD0
2
C/SMBus
11