MAX536 Maxim, MAX536 Datasheet - Page 22

• Manufacturer Part Number: MAX536
• Description: Calibrated / Quad / 12-Bit Voltage-Output DACs with Serial Interface
• Manufacturer: Maxim

In applications where the reference has AC signal compo-
nents, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAB/REFCD. The reference voltage must
never be more negative than DGND.
The MAX536’s total harmonic distortion plus noise
(THD + N) is typically less than 0.012%, given a 5V
nal swing and input frequencies up to 35kHz, or given a
2V
cal -3dB frequency is 700kHz as shown in the Typical
Operating Characteristics graphs.
For the MAX537, with an input signal amplitude of
0.85mV
5k load in parallel with 100pF and input frequencies up to
100kHz, or with a 2k load in parallel with 100pF and input
frequencies up to 95kHz.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Figure 14. When V
Schottky diode between V
22
p-p
______________________________________________________________________________________
swing and input frequencies up to 50kHz. The typi-
p-p
1N5817
, THD + N is typically less than 0.024% with a
SS
and V
SS
3
4
DD
V
AGND
and AGND.
Using an AC Reference
SS
cannot be sequenced, tie a
MAX536
MAX537
p-p
sig-
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage V
where V
to DGND) applied to AGND, and N
value of the DAC’s binary input code. Since AGND is
common to all four DACs, all outputs will be offset by
V
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
On power-up, V
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between V
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
rising edge).
For rated MAX536 performance, V
higher than REFAB/REFCD and should be between
10.8V and 16.5V. When using the MAX537, V
be at least 2.2V higher than REFAB/REFCD and should
be between 4.75V and 5.5V. Bypass both V
with a 4.7 F capacitor in parallel with a 0.1 F capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
BIAS
in the same manner. As the voltage at AGND
Grounding and Layout Considerations
BIAS
is the positive offset voltage (with respect
V
SS
OUTA
Power-Supply Considerations
should come up first, V
= V
BIAS
+ N
B
Offsetting AGND
(V
DD
B
IN)
is the numeric
should be 4V
SS
DD
DD
OUTA
and AGND
DD
next, then
and V
should
is:
SS