MAX5158 Maxim, MAX5158 Datasheet - Page 11

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MAX5158

Manufacturer Part Number
MAX5158
Description
Low-Power / Dual / 10-Bit / Voltage-Output DACs with Serial Interface
Manufacturer
Maxim
Datasheet

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Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
Figure 5. Serial-Interface Timing Diagram
MSB ..................................................................................LSB
Address Bits
Low-Power, Dual, 10-Bit, Voltage-Output DACs
A0
MAX5158
MAX5159
2 Control Bits
1 Address/
SCLK
Control Bits MSB....DataBits...LSB Sub Bits
DIN
CS
C1, C0
SCLK
______________________________________________________________________________________
DIN
16 Bits of Serial Data
CS
A0
1
D9.................. ......D0
C1
10 Data Bits
C0
CPOL = 0, CPHA = 0
MOSI
SCK
I/O
D9
D8
SPI/QSPI
PORT
D7
+5V
SS
D6
S2–S0
000
D5
8
D4
9
The MAX5158/MAX5159’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated and the state of the registers
when exiting shutdown. The 3-bit address/control deter-
mines the following:
• registers to be updated
• clock edge on which data is to be clocked out via
• state of the user-programmable logic output
• configuration of the device after shutdown.
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
D3
the serial-data output (DOUT)
with Serial Interface
D2
D1
D0
S2
S1
S0
16
COMMAND
EXECUTED
11

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