MAX5101 Maxim, MAX5101 Datasheet - Page 6

• Manufacturer Part Number: MAX5101
• Description: +2.7V to +5.5V / Low-Power / Triple / Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs
• Manufacturer: Maxim

+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
The MAX5101 uses a matrix decoding architecture for the
digital-to-analog converters (DACs). The internal refer-
ence voltage is connected to V
resistor string placed in a matrix fashion. Row and col-
umn decoders select the appropriate tab from the resistor
string to provide the needed analog voltages. The resistor
network converts the 8-bit digital input into an equivalent
analog output voltage in proportion to the supply voltage
(V
input impedance to the supply and guarantees a monoto-
nic output.
The voltages are buffered by rail-to-rail op amps con-
nected in a follower configuration to provide a rail-to-rail
output (see Functional Diagram).
The DAC outputs are internally buffered by a precision
amplifier with a typical slew rate of 0.6V/µs. The typical
settling time to ±1/2LSB at the output is 6µs when
loaded with 10kΩ in parallel with 100pF.
The MAX5101’s reference is internally tied to V
output voltage (V
digitally programmable voltage source as follows:
where N
code.
6
5–12
DD
PIN
13
14
15
16
_______________________________________________________________________________________
1
2
3
4
). The resistor string presents a code-independent
B
D7–D0
is the numeric value of the DAC binary input
NAME
OUTB
OUTA
OUTC
GND
V
WR
A1
A0
DD
V
OUT
OUT
DAC B Voltage Output
DAC A Voltage Output
Positive Supply Voltage. Bypass V
Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1.
Data Inputs 7–0
DAC Address Select Bit (MSB)
DAC Address Select Bit (LSB)
Ground
DAC C Voltage Output
) for any DAC is represented by a
= (N
Detailed Description
Digital-to-Analog Section
Output Buffer Amplifiers
DAC Reference Voltage
B
· V
DD
DD
and divided down by a
) / 256
DD
DD
. The
to GND using a 0.1µF capacitor.
In the MAX5101, address lines A0 and A1 select the DAC
that receives data from D0–D7, as shown in Table 1.
When WR is low, the addressed DAC’s input latch is
transparent. Data is latched when WR is high. The DAC
outputs (OUTA, OUTB) represent the data held in the
three 8-bit input latches. To avoid output glitches in the
MAX5101, ensure that data is valid before WR goes low.
The MAX5101 features a software shutdown mode. A
write performed to address A1 = H and A0 = H causes
the device to shut down. A subsequent write to any of
the other three addresses disables shutdown and turns
the analog circuitry on. As the MAX5101 comes out of
shutdown, all registers retain their digital values prior to
shutdown. However, when the device powers up (i.e.,
V
code 00 hex. In shutdown, the output amplifiers enter a
high-impedance state. When bringing the device out of
shutdown, allow 13µs for the output to stabilize.
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass V
located as close to V
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
DD
FUNCTION
ramps up), all latches are internally preset with
Digital Inputs and Interface Logic
Power-Supply Bypassing and
Low-Power Shutdown Mode
DD
and GND as possible.
DD
Ground Management
Pin Description
with a 0.1µF capacitor,