MAX509 Maxim, MAX509 Datasheet - Page 10
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MAX509
Manufacturer Part Number
MAX509
Description
Quad / Serial 8-Bit DACs with Rail-to-Rail Outputs
Manufacturer
Maxim
Datasheet
1.MAX509.pdf
(20 pages)
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Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
10
A1
0
0
1
1
0
0
1
1
X
X
0
1
1
______________________________________________________________________________________
NOTE: TIMING SPECIFICATION t
SCLK
CS
DIN
DOUT
LDAC
A0
X
0
1
0
1
0
1
0
1
0
1
1
0
12-Bit Serial Word
C1
0
0
0
0
1
1
1
1
0
0
1
1
1
t
CSH0
CLL
IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
C0
t
1
1
1
1
1
1
1
1
0
0
0
0
0
CSS
t
DS
t
DH
D7 . . . . . . . . D0
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
t
CH
t
DO
t
CL
LDAC
1
1
1
1
1
1
1
1
X
X
X
X
X
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
Update all DACs from shift register.
No Operation (NOP), shifts data in shift register.
“LDAC” Command, all DACs updated from respective
input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
t
CSH1
t
CSH2
Function
t
CLL
t
LDW