MAX5066 Maxim Integrated Products, MAX5066 Datasheet - Page 13

• Manufacturer Part Number: MAX5066
• Description: Synchronous Buck Controller
• Manufacturer: Maxim Integrated Products

oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
The outer voltage control loop consists of the voltage-
error amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive volt-
age-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
The peak-current comparator (see
the voltage across the current-sense resistor (R
and provides a fast cycle-by-cycle current limit with a
threshold of 52.5mV. Note that the average current-limit
threshold of 22.5mV still limits the output current during
short-circuit conditions. To prevent inductor saturation,
select an output inductor with a saturation current
specification greater than the average current limit of
22.5mV/R
only extreme conditions trip the peak-current compara-
tor, such as a damaged output inductor. The typical
propagation delay of the peak current-limit comparator
is 260ns.
The MAX5066 has two dedicated transconductance
current-error amplifiers CEA1 and CEA2 with a typical
g
ity. The current-error amplifier outputs (CLP1 and CLP2)
serve as the inverting input to the PWM comparators.
CLP1 and CLP2 are externally accessible to provide fre-
quency compensation for the inner current loops (see
C
rent-error amplifier such that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the current-
error amplifier output to a 2V
each clock cycle an R-S flip-flop resets and the high-
side drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminat-
ing the on cycle.
Configurable, Single-/Dual-Output, Synchronous
M
CFF
of 550µS and 320µA output sink and source capabil-
, C
Buck Controller for High-Current Applications
CF
SENSE
, and R
PWM Comparator and R-S Flip-Flop
. Proper inductor selection ensures that
CF
______________________________________________________________________________________
in Figure 2). Compensate the cur-
Peak-Current Comparator
Current-Error Amplifier
P-P
ramp. At the start of
Figure
3) monitors
SENSE
)
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to V
put voltage by connecting a voltage-divider from the
output to EAN_ to GND (see
output of the voltage error amplifier is zero.
Use the equation below to calculate the no load voltage:
The voltage at full load is given by:
where ∆V
described in the Adaptive Voltage Positioning section.
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning
put capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
The internal 0.61V reference in the MAX5066 has a toler-
ance of ±0.9%. If we use 0.1% resistors for R
we still have another 4% available for the variation in the
output voltage from nominal. This available voltage
range allows us to reduce the total number of output
capacitors to meet a given transient response require-
ment. This results in a voltage-positioning window as
shown in Figure 5.
From the allowable voltage-positioning window we can
calculate the value of R
where ∆V
dow, R
sense amplifier gain, and R
SENSE
V
OUT FL
OUT
OUT
(Figure
V
( )
OUT NL
R
is the allowable voltage-positioning win-
is the sense resistor, 36 is the current-
F
is the voltage-positioning window
(
=
Adaptive Voltage Positioning
=
5) reduces the total number of out-
0 6135
)
I
CM
OUT
.
=
F
= 0.61V. Set the MAX5066 out-
0 6135
from the equation below.
×
.
Voltage Error Amplifier
R
1
×
SENSE
∆
is as shown in Figure 4.
⎛
⎜
⎝
V
Figure
1
OUT
×
+
R
R
⎛
⎜
⎝
×
1
2
1
+
36
4). At no load the
⎞
⎟ −
⎠
R
R
×
1
2
∆
R
⎞
⎟
⎠
V
1
OUT
1
and R
13
2
,