TDK-73M2901CL Teridian Semiconductor Corp. (TDK Semiconductor), TDK-73M2901CL Datasheet - Page 3

• Manufacturer Part Number: TDK-73M2901CL
• Description: V.22 BIS Single CHIP Modem
• Manufacturer: Teridian Semiconductor Corp. (TDK Semiconductor)

SPECIFYING A CRYSTAL
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TDK 73M2901CL modem requires a parallel
mode
specifications of which are as follows:
Mode:
Frequency:
Frequency tolerance:
Temperature drift:
Load capacitance:
ESR:
Drive level:
The peak voltage level of the oscillator should be
checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins.
resistor in series with the crystal can be used, if
necessary, to reduce the oscillator’s peak voltage
levels.
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN
NAME
VPA
VNA
VPD
VND
ANALOG INTERFACE PIN DESCRIPTION
PIN
NAME
RXA
TXAN
TXAP
VBG
VREF
(anti-resonant)
6, 25, 29
5, 22, 26
32 pin
32 pin
PLCC
PLCC
An additional ±50 ppm over full range.
15
21
20
16
17
19
18
±50 ppm at initial temperature.
2, 20, 25
1, 17, 22
32 pin
32 pin
TQFP
TQFP
crystal,
10
16
15
11
12
14
13
Parallel (anti-resonant)
11, 24, 44, 28
44 pin LQFP
44 pin LQFP
2, 12, 27, 33
Less than 1mW.
the
18pF or 20pF
11.0592 MHz
16
22
21
17
18
20
19
75 max.
important
A
TYPE
TYPE
O
O
O
O
I
I
I
I
I
3
Crystals with low ESRs may oscillate at higher than
specified voltage levels.
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3 s. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals
for 25ms, acknowledging the reset operation, within
a 250ms time window after the reset-triggering
event. The 73M2901CL is ready for operation after
that 250ms window and/or after the signals
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
The serial data interface consists of the TXD and
RXD data paths (LSB shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
DESCRIPTION
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
DESCRIPTION
Receive Analog input
Transmit Analog - output
Transmit Analog + output
Analog Band Gap voltage reference (0.1 F to
VNA). This pin must not be connected to external
circuitry other than the decoupling capacitor.
Analog reference voltage (0.1 F to VNA)
/
and
V.22bis Single Chip Modem
flow control;
become active.
,
and
,
73M2901CL
will be held inactive
and
. In
,