STK10C68 Simtek Corporation, STK10C68 Datasheet - Page 8

• Manufacturer Part Number: STK10C68
• Description: Density = 64K ;; Format = 8K X 8 ;; # of Pins = 28 ;; Access Time (ns MAX) = 25,35,45 ;; Initiated Store = Hardware ;; Production = Now ;; Volt = 5 ;; Temps Commercial Industrial Military = C/i/m
• Manufacturer: Simtek Corporation

September 2003
STK10C68
The STK10C68 has two modes of operation:
mode and nonvolatile mode, determined by the
state of the NE pin. When in
ory operates as a standard fast static
nonvolatile mode, data is transferred in parallel from
SRAM
Elements to
NOISE CONSIDERATIONS
Note that the STK10C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1 F connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK10C68 performs a
and G are low and NE and W are high. The address
specified on pins A
data bytes will be accessed. When the
ated by an address transition, the outputs will be
valid after a delay of t
READ
at t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
SRAM WRITE
A
low and NE is high. The address inputs must be sta-
ble prior to entering the
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WRITE
ELQV
SS
is initiated by E or G, the outputs will be valid
WRITE
to Nonvolatile Elements or from Nonvolatile
or at t
, using leads and traces that are as short as
cycle is performed whenever E and W are
SRAM
WRITE
GLQV
cycle to avoid data bus contention on
, whichever is later (
WRITE
.
0-12
.
AVQV
determines which of the 8,192
AVQV
access time without the need
or t
WRITE
READ
DVEH
(
READ
SRAM
WLQZ
before the end of an
DVWH
CMOS
cycle whenever E
after W goes low.
mode, the mem-
cycle #1). If the
cycle and must
READ
DEVICE OPERATION
before the end
RAM
0-7
READ
ICs, normal
will be writ-
. While in
cycle #2).
is initi-
SRAM
CC
8
NONVOLATILE STORE
A
low and G is high. While any sequence that
achieves this state will initiate a
ation (
#2) are practical without risking an unintentional
SRAM WRITE
STORE
and the
nonvolatile elements. Once a
ated, further input and output are disabled and the
DQ
If E and G are low and W and NE are high at the end
of the cycle, a
puts will go active, signaling the end of the
NONVOLATILE RECALL
A
low and W is high. Like the
initiated when the last of the four clock signals goes
to the
cycle will take t
inputs are ignored. When the
any
effect.
Internally,
SRAM
information is transferred into the
RECALL
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
As with the
any one control pin to cause a
inadvertent multi-triggering. On power up, once V
exceeds the V
cycle is automatically initiated. Due to this automatic
RECALL
t
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of 4.25V, a
be initiated and will take t
RESTORE
STORE
RECALL
CC
0-7
Document Control # ML0006 rev 0.1
READ
< 3.0V), an internal
pins are tri-stated until the cycle is complete.
STORE
data is cleared, and second, the nonvolatile
RECALL
after V
,
cycle, previous nonvolatile data is erased
operation in no way alters the data in the
SRAM
cycle is performed when NE, E and W and
SRAM
RECALL
cycle is performed when E, G and NE are
or
STORE
that would disturb
WRITE
cycle #1) and E initiation (
CC
CC
READ
contents are then programmed into
state. Once initiated, the
NLQX
exceeds approximately 4.25V.
operation cannot commence until
CC
sense voltage of 4.25V, a
is a two-step procedure. First, the
cycle, a transition must occur on
once again exceeds the sense
RECALL
state on the input pins will take
will be performed and the out-
to complete, during which all
RESTORE
RECALL
STORE
cycle will automatically
STORE
SRAM
STORE
RECALL
to complete.
RECALL
SRAM
cycle,
request will be
data. During a
, only W initi-
cycle is initi-
STORE
, preventing
completes,
RECALL
cells. The
STORE
RECALL
RECALL
cycle
.
CC
is