MAX3540 Maxim Integrated Products, MAX3540 Datasheet - Page 11

• Manufacturer Part Number: MAX3540
• Description: Complete Single-Conversion Television Tuner
• Manufacturer: Maxim Integrated Products

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The MAX3540 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period. It is ready to accept
or send data depending on the R/W bit (Figure 1).
When addressed with a write command, the MAX3540
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX3540 issues an ACK
if the slave address byte is successfully received. The
bus master must then send to the slave the address of
the first register it wishes to write to. If the slave
acknowledges the address, the master can then write
one byte to the register at the specified address. Data
is written beginning with the most significant bit. The
MAX3540 again issues an ACK if the data is success-
fully written to the register. The master can continue to
write data to the successive internal registers with the
MAX3540 acknowledging each successful transfer, or it
can terminate transmission by issuing a STOP condi-
tion. The write cycle does not terminate until the master
issues a STOP condition.
Figure 1. MAX3540 Slave Address Byte
Figure 2. Example: Write registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
Figure 3. Example: Read data from registers 0 through 1.
START
START
SDA
NOTE: TIMING PARAMETERS CONFORM WITH I
SCL
Complete Single-Conversion Television Tuner
110000[ADDR2][ADDR1]
11000[ADDR2][ADDR1]
WRITE DEVICE
WRITE DEVICE
S
ADDRESS
ADDRESS
______________________________________________________________________________________
1
1
R/W
R/W
0
0
ACK
—
ACK
—
2
C BUS SPECIFICATIONS.
1
WRITE 1st REGISTER
2
ADDRESS
WRITE REGISTER
0x00
ADDRESS
0x00
0
3
Write Cycle
ACK
SLAVE ADDRESS
—
ACK
—
START
0
4
WRITE DATA TO
REGISTER 0x00
110000[ADDR2][ADDR1]
0x0E
WRITE DEVICE
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3540 issues an
ACK if the slave address byte is successfully received.
The master then sends the 8-bit address of the first reg-
ister that it wishes to read. The MAX3540 then issues
another ACK. Next, the master must issue a START con-
dition followed by the 7 slave address bits and a read
bit (R/W = 1). The MAX3540 issues an ACK if it success-
fully recognizes its address and begins sending data
from the specified register address starting with the
most significant bit (MSB). Data is clocked out of the
MAX3540 on the rising edge of SCL. On the 9th rising
edge of SCL, the master can issue an ACK and contin-
ue reading successive registers or it can issue a NACK
followed by a STOP condition to terminate transmission.
The read cycle does not terminate until the master
issues a STOP condition. Figure 3 illustrates an example
in which registers 0 and 1 are read back.
0
5
ADDRESS
ACK
ADDR2
—
6
R/W ACK
WRITE DATA TO
REGISTER 0x01
1
0xD8
ADDR1
—
7
READ DATA
D7–D0
REG 0
ACK
—
R/W
8
ACK
—
WRITE DATA TO
REGISTER 0x02
READ DATA
0xE1
D7–D0
REG 1
ACK
9
Read Cycle
NACK
ACK
—
—
STOP
STOP
P
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