TEA1024 Temic Semiconductors (acquired by ATMEL Corporation), TEA1024 Datasheet - Page 2

• Manufacturer Part Number: TEA1024
• Description: Zero Voltage Switch With Fixed RAMp
• Manufacturer: Temic Semiconductors (acquired by ATMEL Corporation)

Power Supply and its Limitations
The voltage limitation contained in the IC allows it to be
powered from mains via series resistance R
fying diode D
The
(see figure 1).
An internal temperature-compensated limiting circuit
protects the module from random peaks of voltage on the
mains, and delivers a defined reference voltage during the
negative half-cycle.
Synchronization
The logic function is synchronized by means of a separate
resistance R
(voltage-synchronization). The width of the pulse can be
varied between wide limits by choice of R
the value chosen, the wider the output pulse is on Pin 5.
Automatic optimization of the phase of the pulse is
necessary, since the latching current of the triac exceeds
the steady current by a factor of 3.
The phase of the pulse is chosen so that ca. 1/3 of the pulse
width appears before the transition through null and 2/3
after it (see electrical characteristics and figure 2).
In order to avoid phase-clipping after the switch-on the
first third of the first pulse is automatically suppressed.
TEA1024/ TEA1124
2 (8)
capacitor
Figure 2. Pulse position optimization
2
1
between Pin 6 (+ Pol/ ) and Pin 4 (–V
connected between Pin 7 and phase
C
1
smooths
the
supply
sync
1
. The larger
and recti–
voltage
S
).
–1.3 V
–3.8 V
95 11410
Full-Wave Logic
The full-wave logic ensures that only pairs of pulses can
be released, and that these always begin with the positive
dv/dt. The load is thus switched on for a minimum of one
complete mains cycle. This means that the triac receives
a minimum of two driving pulses, so that the unwanted
d.c. component in the load circuit is definitely eliminated.
Pulse Amplifier
The pulse amplifier connected to the output of the full-
wave
short-circuits, and delivers negative output pulses of typ.
75 mA, via an integrated limiting resistance, to Pin 5.
Ramp Generator (Figures 3, 4)
Ramp voltage which is generated in the IC is available not
only at reference Pin 1, but also at the non-inverted input
of the comparator.
The current sink which is controlled by D/A converter
influences the internal reference voltage at Pin 1 specified
by voltage divider. The current sink is turned-off in the
reset state of the D/A converter so that the voltage at Pin 1
is primarily specified via the internal voltage divider
(ramp starting voltage).
In the maximum state of the 4 stage (5 stage – TEA1124)
D/A converter, the current sink overtakes the maximum
current, whereby the ramp’s final (end) voltage has
reached. External resistance R
in position to influence the initial ramp voltage as well as
the ramp amplitude. If the external resistances ratio R
R
voltage at the beginning remains maintained (constant),
only the amplitude is compressed.
y
V
1
is the same as that of the internal ratio, the ramp
Figure 3. Ramp diagram without external circuit
logic
(T= 1280 ms)
T= 640 ms
circuit,
TELEFUNKEN Semiconductors
is
proof
x
, R
y
shown in figure 4 are
16 stage ramp
Rev. A1, 24-May-96
against
t
continuos
2.2 V
x
,