CDB61574 Cirrus Logic, Inc., CDB61574 Datasheet - Page 4
CDB61574
Manufacturer Part Number
CDB61574
Description
T1/e1 LINE Interface
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CDB61574.pdf
(44 pages)
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ANALOG SPECIFICATIONS
Notes: 20. For input amplitude of 1.2 V
4
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
Loss of Signal Threshold
Data Decision Threshold
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
Attenuation at 10kHz Jitter Frequency
Attenuator Input Jitter Tolerance (Before Onset
of FIFO Overflow or Underflow Protection)
21. For input amplitude of 0.5 V
22. For input amplitude of 1.05 V
23. Jitter tolerance increases at lower frequencies. See Figure 11.
24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates
jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase
significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section.
T1, DSX-1
T1, DSX-1
T1, (FCC Part 68) and E1 (Note 22)
10kHz - 100kHz
2kHz
10Hz and below
Parameter
pk
pk
pk
(TA = -40 C to 85 C; TV+, RV+ = 5.0V 5%; GND = 0V)
to 4.14 V
to 1.2 V
to 3.3 V
(Notes 17, 24)
(Notes 17, 24)
(Notes 17, 24)
pk
pk
pk
(Note 20)
(Note 21)
(Note 23)
and from 4.14 V
.
.
-13.6
Min
500
160
300
0.4
6.0
60
53
45
12
-
-
pk
-
-
to RV+.
0.30
Typ
50k
175
65
65
50
50
23
6
-
-
-
-
-
Max
190
70
77
55
-
-
-
-
-
-
-
-
-
-
CS61577
% of peak
% of peak
% of peak
DS155PP2
Units
mV
bits
dB
Hz
dB
UI
UI
UI
UI
V
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