CDB61318 Cirrus Logic, Inc., CDB61318 Datasheet - Page 3

• Manufacturer Part Number: CDB61318
• Description: T1/e1 Line Interface Units
• Manufacturer: Cirrus Logic, Inc.

1. POWER SUPPLY
As shown on the evaluation board schematic in
Figure 1, power is supplied to the board from an ex-
ternal +5 Volt supply connected to the two binding
posts labeled V+ and GND. Zener diode Z1 pro-
tects the components on the board from reversed
supply connections and over-voltage damage. Ca-
pacitor C1 provides power supply decoupling and
ferrite bead L1 helps isolate the CS61318 and buff-
er supplies. The 0.1 F capacitors decouple their
respective ICs. Ferrite bead L7 helps isolates the
devices U2, U3 and U4.
2. BOARD CONFIGURATION
Slide switch S1 selects hardware, host or hardware-
coder mode operation by sliding it into HW, SW or
HWCDR positions, respectively.
2.1
In Hardware mode operation, the evaluation board
is configured using the DIP switch SW1. In this
mode, the switch establishes the digital control in-
puts for both line interface channels. Closing a DIP
switch away from the label sets the CS61318 con-
trol pin of the same name to a logic 1. The host pro-
cessor interface J1 should not be used in the
Hardware mode.
The CDB61318 switches and functions are listed
below:
All switch inputs are pulled-high using resistor R13
when the switch is closed.
2.1.1
NLOOP is enabled in the hardware mode by short-
ing HDR11 (HW_NLOOP) and then pressing S2. It
can also be done by closing the switches RLOOP,
LLOOP and TAOS on SW1, pulling them high,
DS441DB1
– TAOS: transmit all ones;
– LLOOP: local loopback;
– RLOOP: remote loopback;
– JASEL: jitter attenuator path selection;
Hardware Mode
Network Loopback
and then pulling them back to low by opening the
RLOOP, LLOOP and TAOS switches. NLOOP
can then be turned on by sending the 1:4 pattern to
the receive input RTIP and RRING for five sec-
onds. The NLOOP LED will light up at this point if
HDR6 is jumped to NLOOP_LED position.
NLOOP can be turned off by sending a 1:2 pattern
to RTIP and RRING for five seconds.
2.2
This mode is essentially the same as the Hardware
mode with the HDB3 encoder/decoder enabled.
2.3
In Host mode operation, the evaluation board sup-
ports serial-port operation over interface port J1 us-
ing the printer port of a host PC running the enclosed
software. The evaluation board is connected to the
host PC using a standard DB-25 male-to-female ca-
ble (included). Ferrite beads L2-L6 help reduce in-
coming noise from the host interface. The SW1
switch must be open to enable serial port operation.
An external microprocessor may also interface to
the serial port of the CS61318 through HDR12.
HDR6 must be jumpered so the interrupt pin, INT,
Comes out to HDR12.
3. TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on
BNC inputs labeled TCLK, TPOS, and TNEG. In
Hardware and Host mode (with coder mode dis-
abled), data is supplied on the TPOS and TNEG
BNC inputs. In Host mode with coder mode en-
abled, data is supplied on the TDATA BNC input.
The transmitter output is transformer coupled to the
line through the step-up transformer T2. The signal
is available at either the Transmit binding posts
(J11, J13) or the Transmit bantam jack. Capacitor
C12 prevents output stage imbalances from pro-
ducing a DC current that may saturate the trans-
former, thus degrading its performance.
Hardware-Coder Mode
Host Mode
CDB61318
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