CDB61310 Cirrus Logic, Inc., CDB61310 Datasheet - Page 3

• Manufacturer Part Number: CDB61310
• Description: T1/e1 Line Interface Units
• Manufacturer: Cirrus Logic, Inc.

1. POWER SUPPLY
As shown on the evaluation board schematic in
Figure 1, power is supplied to the board from an ex-
ternal +5 Volt supply connected to the two binding
posts labeled V+ and GND. Zener diode Z1 pro-
tects the components on the board from reversed
supply connections and over-voltage damage. Ca-
pacitor C1 provides power supply decoupling and
ferrite bead L1 helps isolate the CS61310 and buff-
er supplies. The 0.1 F capacitors decouple their re-
spective ICs. Ferrite bead L7 helps isolates the +5V
power into the board.
2. BOARD CONFIGURATION
Slide switch S1 selects hardware, host or hardware-
coder mode operation by sliding it into HW, SW or
HWCDR positions, respectively.
2.1
In Hardware mode operation, the evaluation board
is configured using the DIP switch SW1. In this
mode, the switch establishes the digital control in-
puts for both line interface channels. Closing a DIP
switch away from the label sets the CS61310 con-
trol pin of the same name to a logic 1. The host pro-
cessor interface J1 should not be used in the
Hardware mode.
The CDB61310 switches and functions are listed
below:
All switch inputs are pulled high through resistor
R13 when the switch is closed.
2.1.1
NLOOP is enabled in the hardware mode by short-
ing HDR11 (HW_NLOOP) and then pressing S2.
NLOOP can also be enabled by closing the switch-
DS440DB2
– TAOS: transmit all ones;
– LLOOP: local loopback;
– RLOOP: remote loopback;
– JASEL: jitter attenuator path selection;
– LBO1, LBO2: line build out settings.
Hardware Mode
Network Loopback
es RLOOP, LLOOP and TAOS on SW1, pulling
them high, and then pulling them back to low by
opening the RLOOP, LLOOP and TAOS switches
in that order. NLOOP can then be turned on by
sending the 1:4 pattern to the receive input (RTIP
and RRING) for five seconds. If HDR6 is jumped
to the NLOOP_LED position, the NLOOP LED
will light up. NLOOP can be turned off by sending
a 1:2 pattern to RTIP and RRING for five seconds.
2.2
This mode is essentially the same as the Hardware
mode with the B8ZS encoder/decoder enabled.
2.3
In Host mode operation, the evaluation board can be
accessed by a PC through the parallel printer port.
Connector J1 on the evaluation board is connected to
the host PC using a standard DB-25 male-to-female
cable (included). Ferrite beads L2 through L6 help
reduce noise coming from the PC. The SW1 switch
must be open to allow serial port operation.
An external microprocessor may also interface to
the serial port of the CS61310 through HDR12. In
this mode HDR6 should be jumpered so the INT
pin comes out at HDR12.
3. TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on
BNC inputs labeled TCLK, TPOS, and TNEG. In
Hardware and Host mode (with coder mode dis-
abled), data is supplied on the TPOS and TNEG
BNC inputs. In Host mode with coder mode en-
abled, data is supplied on the TDATA BNC input.
The transmitter output is transformer coupled to the
line through the step-up transformer T2. The signal
is available at the Transmit test points, binding
posts (J11, J13) or the Transmit bantam jack. Ca-
pacitor C12 prevents output stage imbalances from
producing a DC current that may saturate the trans-
former, thus degrading its performance.
Hardware-Coder Mode
Host Mode
CDB61310
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