ADS-117 Datel, Inc., ADS-117 Datasheet - Page 3

• Manufacturer Part Number: ADS-117
• Description: 2mhz, Low-power ADC: 12-bit
• Manufacturer: Datel, Inc.

TECHNICAL NOTES
1. Applications which are unaffected by endpoint errors or
2. Always connect the analog and digital grounds to a ground
3. Bypass the analog and digital supplies and the +10V
4. Obtain straight binary/offset binary output coding by tying
remove them through software will use the typical connec-
tions shown in Figure 3. Remove system errors or adjust
the small initial errors of the ADS-117 to zero using the
optional external circuitry shown in Figure 4. The external
adjustment circuit has no effect on the throughput rate.
plane beneath the converter for best performance. The
analog and digital grounds are not connected to each other
internally.
reference (pin 21) to ground with 4.7µF, 25V tantalum
electrolytic capacitors in parallel with 0.1µF ceramic
capacitors. Bypass the +10V reference (pin 21) to
ANALOG GROUND (pin 23).
COMP BIN (pin 18) to +5V or leaving it open. The device
has an internal pull-up resistor on this pin. To obtain
complementary binary or complementary offset binary
®
INTERNAL S/H
CONVERT
OUTPUT
START
DATA
EOC
Note: Scale is approximately 25ns per division.
®
DATA N-1 VALID
N
350ns min.
10ns min.
25ns max.
10ns min.
17ns max.
50ns typ.,
30ns min., 60ns max.
Conversion Time
Hold
325ns typ.
Figure 2. ADS-117 Timing Diagram
150ns max.
INVALID
DATA
Acquisition Time
170ns max.
165ns typ.
3
5. To enable the three-state outputs, connect ENABLE (pin 17)
6. To meet the guaranteed conversion rate, a maximum start
7. Re-initiating the START CONVERT (pin 16) while EOC is a
output coding, tie pin 18 to ground. The pin 18 signal is
compatible with CMOS/TTL logic levels for those users
desiring dynamic control of this function. Do not change
COMP BIN status while EOC is high.
to a logic "0" (low). To disable, connect pin 17 to a logic "1"
(high).
convert pulse is specified. A wider start convert pulse will
result in slower conversion rates. An initial start convert
pulse is required before performing an actual conversion
after power-up to assure the sample-hold is in the acquisi-
tion mode.
Figure 2 shows the relationship between the various input
signals. The timing shown applies over the operating
temperature range and over the operating power supply
range.
logic "1" (high) will result in a new conversion sequence.
60ns max.
35ns max.
N+1
DATA N VALID
INVALID
DATA
ADS-117