MAX17491 Maxim Integrated Products, MAX17491 Datasheet - Page 10

• Manufacturer Part Number: MAX17491
• Description: Single-Phase Synchronous MOSFET Driver
• Manufacturer: Maxim Integrated Products

Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the
switching-loss equation above. If the high-side MOSFET
chosen for adequate R
becomes extraordinarily hot when biased from V
consider choosing another MOSFET with lower parasitic
capacitance.
For the low-side MOSFET (N
dissipation always occurs at the maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
I
the current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle
the overload power dissipation. The heatsink can be a
large copper field on the PCB or an externally mounted
device.
An optional Schottky diode only conducts during the
dead time when both the high-side and low-side
MOSFETs are off. Choose a Schottky diode with a
forward voltage low enough to prevent the low-side
MOSFET body diode from turning on during the dead
time, and a peak current rating higher than the peak
inductor current. The Schottky diode must be rated to
handle the average power dissipation per switching
cycle. This diode is optional and can be removed if effi-
ciency is not critical.
Power dissipation in the IC package comes mainly from
driving the MOSFETs. Therefore, it is a function of both
switching frequency and the total gate charge of the
selected MOSFETs. The total power dissipation when
both drivers are switching is given by:
where I
lated in the 5V Bias Supply (V
die temperature due to self-heating is given by the
following formula:
Single-Phase Synchronous MOSFET Driver
10
LOAD(MAX)
PD N RESISTIVE
(
______________________________________________________________________________________
L
BIAS
, but are not quite high enough to exceed
is the bias current of the 5V supply calcu-
)
PD IC
=
⎡
⎢
⎢
⎣
( ) =
1
IC Power Dissipation and
−
DS(ON)
Thermal Considerations
⎛
⎜
⎝
V
IN MAX
I
V
BIAS
OUT
(
L
), the worst-case power
DD
at low battery voltages
× 5
)
⎞
⎟
⎠
) section. The rise in
⎤
⎥
⎥
⎦
V
⎛
⎜
⎝
η
I
LOAD
TOTAL
⎞
⎟
⎠
2
R
IN(MAX)
DS ON
(
)
,
where PD(IC) is the power dissipated by the device,
and θ
cal thermal resistance is 42°C/W for the 3mm x 3mm
TQFN package.
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the low-
side MOSFET. The high dV/dt causes a current flow
through the Miller capacitance (C
capacitance (C
selection of the low-side MOSFET that results in a high
ratio of C
avoid this problem, minimize the ratio of C
when selecting the low-side MOSFET. Adding a 1Ω to
4.7Ω resistor between BST and C
high-side MOSFET turn-on. Similarly, adding a small
capacitor from the gate to the source of the high-side
MOSFET has the same effect. However, both methods
work at the expense of increased switching losses.
The MAX17491 MOSFET driver sources and sinks large
currents to drive MOSFETs at high switching speeds.
The high di/dt can cause unacceptable ringing if the
trace lengths and impedances are not well controlled.
The following PCB layout guidelines are recommended
when designing with the MAX17491:
1) Place all decoupling capacitors as close as possi-
2) Minimize the length of the high-current loop from
3) Provide enough copper area at and around the
4) Connect GND of the MAX17491 as close as possi-
A sample layout is available in the MAX17030 evaluation
kit.
ble to their respective IC pins.
the input capacitor, the upper switching MOSFET,
and the low-side MOSFET back to the input-capacitor
negative terminal.
switching MOSFETs and inductors to aid in thermal
dissipation.
ble to the source of the low-side MOSFETs.
JA
is the package’s thermal resistance. The typi-
RSS
/C
ISS
ISS
Avoiding dV/dt Turning on the
ΔT
) of the low-side MOSFET. Improper
makes the problem more severe. To
J
=
θ
JA
×
PD IC
Low-Side MOSFET
Layout Guidelines
( )
RSS
BST
www.DataSheet4U.com
) and the input
can slow the
RSS
/C
ISS