ATA6829 ATMEL Corporation, ATA6829 Datasheet - Page 4

• Manufacturer Part Number: ATA6829
• Description: Dual Triple DMOS Output Driver with Serial Input Control
• Manufacturer: ATMEL Corporation

3. Functional Description
3.1
Figure 3-1.
4
Serial Interface
CLK
DO
CS
T6819/ATA6829
DI
Data Transfer
SRR
0
TP
1
S1L
LS1
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-
ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS
is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output
data will change their state with the rising edge of CLK and stay stable until the next rising edge
of CLK appears. LSB (bit 0, TP) is transferred first.
Table 3-1.
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
S1H
HS1
2
Input Register
3
S2L
LS2
Input Data Protocol
S2H
HS2
4
OCS
SRR
OLD
HS1
HS2
HS3
PH1
PH2
PH3
LS1
LS2
LS3
PL1
PL2
PL3
SI
5
S3L
LS3
S3H
6
HS3
Function
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Output LS1 additionally controlled by PWM Input
Output HS1 additionally controlled by PWM Input
See PL1
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part
is still powered)
n. u.
7
PL1
n. u.
8
PH1
9
n. u.
PL2
10
n. u.
PH2
11
n. u.
PL3
12
n. u.
PH3
13
OVL
OLD
14
OCS
INH
15
PSF
SI
4531F–BCD–09/05