MAX15041 Maxim Integrated Products, MAX15041 Datasheet - Page 12

• Manufacturer Part Number: MAX15041
• Description: Step-Down DC-DC Regulator
• Manufacturer: Maxim Integrated Products

Low-Cost, 3A, 4.5V to 28V Input, 350kHz, PWM
Step-Down DC-DC Regulator with Internal Switches
Figure 1. Peak Current-Mode Regulator Transfer Model
Having defined the power modulator’s transfer function
gain, the total system loop gain can be written as fol-
lows (see Figure 1):
where R
gain, A
ductance, g
much larger than C
Rewriting:
12
α =
Gain
FEEDBACK
R
R
DIVIDER
1
2
V
OUT
⎡ ⎣
______________________________________________________________________________________
s C
=
×
(
VEA
V
G
C
β
OUT
V
OUT
MOD LOAD
=
+
FB
REF
G
, divided by the error amplifier’s transcon-
C
FB
MV
MOD
CC
is the quotient of the error amplifier’s DC
A
R
; R
)
Gain
VEA
g
(
R
MV
×
C
OUT
R
CC
+
=
×
LOAD
ERROR AMPLIFIER
*C
R
R
×
⎡
⎢
⎣
R
OUT
CC
.
1
is much larger than R
sC
R
⎡ ⎣
OUT
OUT
R
s s C
IS OPTIONAL.
+ +
×
2
C
)
= A
+
⎡ ⎣
R
OUT
×
R
⎛
⎝ ⎜
sC
1
2
OUT
(
VEA
A
(
⎤ ⎦ ×
sC R
g
sC
OUT
×
VEA
MV
/g
R
A
(
⎡ ⎣
(
C C
MV
ESR R
sC
OUT
s C
OUT
(
VEA
sC R
(
(
ESR R
O
⎞
⎠ ⎟
C C
+
U U T
C C
R
+
ESR
C
×
+
C
1
||
C
1 1
ESR
)
α β
+
COMP
C
⎤
⎥ ×
⎦
×
LOAD
CC
LOAD
+
+
(
+
*C
1
1
)(
sC
1
)
)
R
)
CC
C
CC C
)
)
C
+
+
||
1
and C
R
⎤ ⎦ 1
R
⎤ ⎦
NOTE: THE G
THE INDUCTOR INJECTED INTO THE OUTPUT LOAD. THIS REPRESENTS A
SIMPLIFICATION FOR THE POWER MODULATOR STAGE DRAWN ABOVE.
OUT
Σ
+
COMPARATOR
)
1
+
)
C
PWM
1
⎤ ⎦
is
MOD
STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
COMPENSATION
The dominate poles and zeros of the transfer loop gain
is shown below:
The order of pole-zero occurrence is:
Note under heavy load, f
A graphical representation of the asymptotic system
closed-loop response, including the dominant pole and
zero locations is shown in Figure 2.
g
MC
CONTROL
f
f
f
P
P
Z
RAMP
LOGIC
V
1
3
2
COMP
=
=
POWER MODULATOR
=
2
2
2
π
π
π π × C
×
×
G
10
MOD
C
1
CC C
OUT
AVEA dB
1
R
g
ESR
MV
V
_
IN
V
f
P
OUT
I
L
Q
Q
1
HS
LS
f
Z
/
<
20
1
f
P
=
L0
×
2
2
C
π
<
P2
C
×
f
Z
, may approach f
C R
1
1
C C
f
P
<
DCR
2
I
L
f
=
Z
2
2
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π
≤
×
f
P
C
3
OUT
C
ESR
OUT
OUTPUT FILTER
AND LOAD
(
ESR
1
Z1
.
V
+
OUT
R R
LOAD
R
LOAD
)