MAX15021 Maxim Integrated Products, MAX15021 Datasheet - Page 14

• Manufacturer Part Number: MAX15021
• Description: Step-Down DC-DC Regulator
• Manufacturer: Maxim Integrated Products

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Use the following equation to calculate the input ripple
when only one regulator is enabled:
The MAX15021 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use additional
bulk capacitance if the input source impedance is high. If
using a lower input voltage, additional input capacitance
helps to avoid possible undershoot below the undervolt-
age lockout threshold during transient loading.
The allowed output-voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of ΔV
the capacitor discharge) and ΔV
voltage drop across the equivalent series resistance of
the output capacitor). The equations for calculating the
output capacitance and its ESR are:
where ΔI
f
ΔV
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, ΔV
using electrolytic capacitors, ΔV
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with an
increased duty cycle. The response time (t
depends on the gain bandwidth of the controller (see
the Compensation-Design Guidelines section). The
resistive drop across the output capacitor’s ESR
(ΔV
and the capacitor discharge (ΔV
droop during the load-step (I
of low-ESR tantalum/aluminum electrolyte and ceramic
capacitors for better load transient and voltage ripple
performance. Nonleaded capacitors and capacitors in
parallel help reduce the ESL. Keep the maximum out-
Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Tracking/Sequencing Capability
14
SW
ESR
ESR
is the switching frequency.
I
______________________________________________________________________________________
CIN(RMS)
and ΔV
), the drop across the capacitor’s ESL (ΔV
P-P
C
OUT
is the peak-to-peak inductor current, and
[A] I
Q
ESR m
[
are not directly additive since they are
μ =
=
F
[
]
LOAD(MAX)
V
Output-Capacitor Selection
OUT_
Ω
8
]
×
=
Δ
2
[V]
V [V] f
×
Q
Δ
Δ
Δ
×
STEP
V
I
[A]
V
I
P P
P P
(
PVIN_
ESR
V
−
ESR
−
×
PVIN_
×
[A]
). Use a combination
[A]
ESR
SW
Q
[mV]
dominates.
[V]
) cause a voltage
[MHz]
−
(caused by the
Q
V
Q
OUT_
dominates. If
(caused by
RESPONSE
)
[V]
ESL
),
)
put voltage deviation below the tolerable limits of the
electronics being powered.
Use the following equations to calculate the required
output capacitance, ESR, and ESL for minimal output
deviation during a load step:
where I
load step, and t
controller.
The MAX15021 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by
comparing the output voltage against a fixed reference.
The subsequent “error” voltage that appears at the
error-amplifier output (COMP_) is compared against an
internal ramp voltage to generate the required duty
cycle of the pulse-width modulator. A second-order
lowpass LC filter removes the switching harmonics and
passes the DC component of the pulse-width-modulat-
ed signal to the output. The LC filter has an attenuation
slope of -40dB/decade and introduces 180° of phase
shift at frequencies above the LC resonant frequency.
This phase shift in addition to the inherent 180° of
phase shift of the regulator’s negative feedback system
turns the feedback into unstable positive feedback. The
error amplifier and its associated circuitry must be
designed to achieve a stable closed-loop system.
The basic controller loop consists of a power modulator
(comprised of the regulator’s pulse-width modulator,
associated circuitry, and LC filter), an output feedback
divider, and an error amplifier. The power modulator has
a DC gain set by V
(V
DC gain of 4V/V, providing effective feed-forward com-
pensation of input-voltage supply DC variations. The
feed-forward compensation eliminates the dependency
of the power modulator’s gain on the input voltage such
that the feedback compensation of the error amplifier
requires no modifications for nominal input-voltage
changes. The output filter is effectively modeled as a
double-pole and a single zero set by the output induc-
tance (L), the DC resistance of the inductor (DCR), the
output capacitance (C
resistance (ESR).
RAMP
STEP
) is a function of the V
C
OUT
ESL
is the load step, t
Compensation-Design Guidelines
[
[
μ
nH
ESR m
RESPONSE
F
]
]
AVIN
=
=
[
I
STEP
Δ
Ω
V
/V
OUT
ESL
]
RAMP
=
[A] t
is the response time of the
) and its equivalent series
Δ
[mV] t
I
I
STEP
V
AVIN
STEP
STEP
×
Δ
ESR
V [V]
where the ramp voltage
RESPONSE
Q
×
[A]
[mV]
[A]
and results in a fixed
is the rise time of the
STEP
[ ]
μ
s
[ ]
μ
s