MAX148 Maxim, MAX148 Datasheet - Page 11

• Manufacturer Part Number: MAX148
• Description: +2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs
• Manufacturer: Maxim

Table 3. Channel Selection in Differential Mode (SGL/D D I I F F = 0)
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
SEL2
1) Set up the control byte for external clock mode and
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB1 and, simultaneously, receive a byte
4) Transmit a byte of all zeros ($00 hex) and, simulta-
5) Transmit a byte of all zeros ($00 hex) and, simulta-
6) Pull CS high.
SSTRB
0
0
0
0
1
1
1
1
DOUT
A/D STATE
SCLK
DIN
CS
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
CS low.
and call it RB1. Ignore RB1.
neously, receive byte RB2.
neously, receive byte RB3.
SEL1
0
0
1
1
0
0
1
1
START
1
SEL2 SEL1 SEL0
______________________________________________________________________________________
SEL0
+2.7V to +5.25V, Low-Power, 8-Channel,
IDLE
0
1
0
1
0
1
0
1
RB1
4
UNI/
BIP
Simple Software Interface
CH0
SGL/
(f
DIF
ACQUISITION
+
SCLK
–
1.5 s
t
ACQ
PD1
= 2MHz)
PD0
8
CH1
+
–
MSB
B9
CH2
B8
+
–
B7
12
RB2
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three trail-
ing zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
The MAX148/MAX149 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
B6
CONVERSION
B5
CH3
+
–
B4
Serial 10-Bit ADCs
B3
16
CH4
+
–
B2
B1
CH5
LSB
B0
+
–
S1
20
RB3
S0
CH6
FILLED WITH
ZEROS
+
–
IDLE
Clock Modes
Digital Output
SCLK
24
CH7
+
–
≤ 2MHz)
11