XR17D154 Exar Corporation, XR17D154 Datasheet - Page 43

• Manufacturer Part Number: XR17D154
• Description: Four-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. P1.0.0
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input
when the modem interface is not used.
MODEM STATUS REGISTER (MSR) - WRITE ONLY
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]: Programmable RS485 Turn-around Delay
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks.
SCRATCH PAD REGISTER (SPR)
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
FEATURE CONTROL REGISTER (FCTR)
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
T
ABLE
15: A
UTO
Table 15
MSR[7]
RS485 H
0
0
0
0
0
9
0
0
1
1
1
1
1
1
1
1
shows the selection. The bits are enabled by EFR bit-4.
MSR[6]
ALF
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-
DUPLEX
MSR[5]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
IRECTION
MSR[4]
43
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
ONTROL
D
ELAY IN
D
ELAY FROM
D
ATA
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
B
IT
T
(
S
RANSMIT
) T
IME
PRELIMINARY
-
TO
áç
áç
áç
áç
-R
ECEIVE