XR16L788 Exar Corporation, XR16L788 Datasheet - Page 10

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

T
A 16-bit down-count timer for general purpose timer
or counter. Its clock source may be selected from in-
ternal crystal oscillator or externally on pin TMRCK.
The timer can be set to be a single-shot for a one-
time event or re-triggerable for a periodic event. An
T
P
[TIMERMSB, TIMELSB, TIMER, TIMECNTL]
(
TIMERCNTL [0]
TIMERCNLT [1]
TIMERCNTL [2]
TIMERCNTL [3]
TIMERCNTL [7:4]
ABLE
1.1.2 General Purpose 16-bit Timer/Counter.
DEFAULT
ABLE
RIORITY
1
2
3
4
5
6
7
x
F
3: UART C
4: TIMER CONTROL R
IGURE
B
T IM E R C N T L [3 ]
0
0
0
0
1
1
1
1
T IM E R C N T L [1 ]
T IM E R C N T L [2 ]
T IM E R C N T L [0 ]
IT
T IM E R M S B a n d T IM E R L S B
O S C . C L O C K
2B
0
X
5. T
IT
XX-XX-00-00)
0
0
1
1
0
0
1
1
1 B
T M R C K
(1 6 -b it V a lu e )
IMER
HANNEL
IT
0 None
1 RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX
0 RXRDY Time-out: Cleared same way as RXRDY INT.
1 TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
0 MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two clears
1 Reserved.
0 Reserved.
1 TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register.
Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
Reserved (defaults to zero).
0
FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register.
after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR register.
Reserved in other channels.
/C
OUNTER CIRCUIT
T im e r In te rru p t E n a b le
S ta rt/S to p
S in g le /R e -trig g e ra b le
C lo c k
S e le c t
[7:0] I
1
0
EGISTER
NTERRUPT
.
T im e r/C o u n te r
S
OURCE
1 6 -B it
I
NTERRUPT
R e -trig g e r
E
NCODING AND
10
0
1
interrupt may be generated in the INT Register when
the timer times out. It is controlled through 4 configu-
ration registers [TIMERCNTL, TIMER, TIMELSB,
TIMERMSB]. These registers provide start/stop and
re-triggerable or one-shot operation. The time-out
output of the Timer can be set to generate an inter-
rupt for system or event alarm.
T im e -o u t
S in g le -s h o t
S
OURCE
C
(
S
1
0
LEARING
)
AND
C
N o In te rru p t
T im e r In te rru p t, C h -0 IN T = 7
LEARING
XR16L788 OCTAL UART
REV. 1.1.4