MAX+PLUSII Altera Corporation, MAX+PLUSII Datasheet - Page 12

• Manufacturer Part Number: MAX+PLUSII
• Description: Programmable Logic Development System & Software
• Manufacturer: Altera Corporation

MAX+PLUS II Programmable Logic Development System & Software Data Sheet
668
Timing-Driven Compilation
The Compiler can implement user-specified timing requirements for
propagation delays (t
and clock frequency (f
on selected logic functions and for a project as a whole. The Report File
and Compiler messages provide detailed information on how the timing
requirements have been implemented in the project.
Design-Rule Checking
The MAX+PLUS II Compiler includes the Design Doctor, a design-rule
checker. The Design Doctor checks each design file for logic that may
cause system-level reliability problems that are usually discovered only
after a design has entered production. The user can choose one of three
predefined sets of design rules, or create a custom set of rules.
Design rules are based on reliability guidelines that cover potential design
problems such as asynchronous inputs, ripple clocks, multi-level logic on
clocks, preset and clear configurations, and race conditions. Rule
violations are explained to help the designer determine which edits are
needed in the design files.
Multi-Device Partitioning
If a project is too large to fit in a single device, the Compiler’s Partitioner
module divides it into multiple devices from the same device family. The
Partitioner attempts to split the project into the fewest possible number of
devices while minimizing the number of pins used for inter-device
communication. The Fitter automatically fits the logic into the specified
devices.
Partitioning can be totally automatic, partially user-controlled, or fully
user-controlled. If a project is too large to fit into the target device, the
designer can specify the type and number of additional devices.
Industry-Standard Simulation Formats
The MAX+PLUS II Compiler can create netlist files for use in a variety of
simulation environments. These netlist files contain post-synthesis
functional and timing information that can be used with standard design
verification tools for device- or board-level simulation.
PD
MAX
), clock-to-output delays (t
). Designers can specify timing requirements
CO
), setup times (t
Altera Corporation
SU
),