MAX114 Maxim, MAX114 Datasheet - Page 7

• Manufacturer Part Number: MAX114
• Description: +5V / 1Msps / 4 & 8-Channel / 8-Bit ADCs with 1A Power-Down
• Manufacturer: Maxim

The MAX114/MAX118 use a half-flash conversion tech-
nique (see Functional Diagram ) in which two 4-bit flash
ADC sections achieve an 8-bit result. Using 15 com-
parators, the flash ADC compares the unknown input
voltage to the reference ladder and provides the upper
four data bits. An internal digital-to-analog converter
(DAC) uses the four most significant bits (MSBs) to
generate both the analog result from the first flash con-
version and a residue voltage that is the difference
between the unknown input and the DAC voltage. The
residue is then compared again with the flash com-
parators to obtain the lower four data bits (LSBs).
An internal analog multiplexer enables the devices to
read four (MAX114) or eight (MAX118) different analog
voltages under microprocessor (µP) control. One of the
MAX118’s analog channels, IN8, is internally hard-
wired and always reads V
Figure 1. Load Circuits for Data-Access Time Test
Figure 2. Load Circuits for Data-Hold Time Test
_______________Detailed Description
OUTPUTS
OUTPUTS
R
DATA
DATA
L
= 3k
3k
a) HIGH-Z TO V OH
a) V OH TO HIGH-Z
_______________________________________________________________________________________
REF+
C
10pF
L
OUTPUTS
OUTPUTS
Converter Operation
DATA
DATA
when selected.
8-Bit ADCs with 1µA Power-Down
b) HIGH-Z TO V OL
b) V OL TO HIGH-Z
V
V
DD
DD
R
L
3k
C
10pF
= 3k
L
+5V, 1Msps, 4 & 8-Channel,
In burst-mode or low sample-rate applications, the
MAX114/MAX118 can be shut down between conver-
sions, reducing supply current to microamp levels (see
Typical Operating Characteristics ). A logic low on the
PWRDN pin shuts the devices down, reducing supply
current typically to 1µA when powered from a single +5V
supply. A logic high on PWRDN wakes up the
MAX114/MAX118, and the selected analog input enters
the track mode. The signal is fully acquired after 360ns
(this includes both the power-up delay and the track/hold
acquisition time), and a new conversion can be started.
If the power-down feature is not required, connect
PWRDN to V
digital inputs at the supply rails in power-down mode.
Refer to the Reference section for information on reduc-
ing reference current during power-down.
The MAX114/MAX118 have two basic interface modes,
which are set by the MODE pin. When MODE is low,
the converters are in read mode; when MODE is high,
the converters are set up for write-read mode. The A0,
A1, and A2 inputs control channel selection, as shown
in Table 1. The address must be valid for a minimum
time, t
Table 1. Truth Table for Input Channel
Selection
In read mode, conversions and data access are con-
trolled by the RD input (Figure 3). The comparator
inputs track the analog input voltage for the duration of
t
With µPs that can be forced into a wait state, hold RD
low until output data appears. The µP starts the conver-
sion, waits, and then reads data with a single read
instruction.
ACQ
___________________Digital Interface
A1
—
—
—
—
MAX114
0
0
1
1
. Initiate a conversion by driving CS and RD low.
ACQ
A0
—
—
—
—
0
1
0
1
, before the next conversion starts.
DD
. For minimum current consumption, keep
A2
0
0
0
0
1
1
1
1
MAX118
A1
0
0
1
1
0
0
1
1
Read Mode (MODE = 0)
A0
0
1
0
1
0
1
0
1
Power-Down Mode
(reads V
SELECTED CHANNEL
REF+
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
if selected)
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