MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 7

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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AC ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude at -1dBFS differential, clock input amplitude 400mV
are at T
Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
Note 3: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
Note 4: The offset-adjust control input is tied to an internal 1.25V reference level through a resistor.
Note 5: Measured with the positive supplies tied to the same potential, V
Note 6: To achieve 2.8GHz full-power bandwidth, careful board layout techniques are required.
Note 7: The total harmonic distortion (THD) is computed from the second through the 15th harmonics.
Note 8: Guaranteed by design and characterization.
Note 9: RSTOUTP/RSTOUTN are tested for functionality.
(V
input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential R
values are at T
LVDS Output Rise Time
LVDS Output Fall Time
LVDS Differential Skew
PortD Data Pipeline Delay
PortC Data Pipeline Delay
PortB Data Pipeline Delay
PortA Data Pipeline Delay
CC
CC
-10
-20
-30
-40
-50
-60
-70
-80
-90
A = V
A = V
0
FFT PLOT (16,384-POINT DATA RECORD)
A
0
scale range (FSR) is defined as 255 x slope of the line where the slope of the line is determined by the end-point code tran-
sitions. When the analog input voltage exceeds positive FSR, the output code is 11111111; when the analog input voltage is
beyond the negative FSR, the output code is 00000000.
common-mode voltage, expressed in dB.
138.24
= +25°C, unless otherwise noted.)
CC
CC
PARAMETER
ANALOG INPUT FREQUENCY (MHz)
I = V
I = V
276.48
J
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
= +105°C, unless otherwise noted.)
CC
CC
414.72
D = 5V, V
D = 5V, V
_______________________________________________________________________________________
552.96
691.20
f
f
A
SNR = 45.2dB
SINAD = 44.8dB
THD = -55.7dBc
SFDR = 57.2dBc
HD2 = -69.6dBc
HD3 = -57.2dBc
CLK
IN
IN
= 98.145MHz
= -0.975dBFS
= 2.21184GHz
CC
CC
829.44
O = 3.3V, V
O = 3.3V, V
967.68
and 1:4 Demultiplexed LVDS Outputs
SYMBOL
1105.92
t
t
t
RDATA
SKEW1
FDATA
t
t
t
t
PDD
PDC
PDB
PDA
EE
EE
= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f
= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f
-10
-20
-30
-40
-50
-60
-70
-80
-90
20% to 80%, C
20% to 80%, C
Any two LVDS output signals, except DCO
0
FFT PLOT (16,384-POINT DATA RECORD)
0
138.24
ANALOG INPUT FREQUENCY (MHz)
276.48
P-P
414.72
L
L
CONDITIONS
differential, digital output pins differential R
< 2pF
< 2pF
552.96
Typical Operating Characteristics
691.20
f
f
A
SNR = 45.1dB
SINAD = 44.8dB
THD = -56.2dBc
SFDR = 62.4dBc
HD2 = -64.4dBc
HD3 = -62.7dBc
CLK
IN
IN
CC
= 300.105MHz
= -1.034dBFS
= 2.21184GHz
829.44
A = V
967.68
CC
1105.92
D = V
CC
I. V
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
CC
FFT PLOT (16,384-POINT DATA RECORD)
0
MIN
138.24
varies from 4.75V to 5.25V.
f
f
A
SNR = 44.5dB
SINAD = 43.3dB
THD = -49.5dBc
SFDR = 52.1dBc
HD2 = -57.3dBc
HD3 = -52.1dBc
CLK
IN
IN
= 999.135MHz
ANALOG INPUT FREQUENCY (MHz)
= -1.059dBFS
= 2.21184GHz
276.48
CLK
CLK
<100
TYP
10.5
500
500
414.72
7.5
8.5
9.5
L
= 2.21184Gsps, analog
= 2.2Gsps, analog input
= 100Ω. Typical values
L
552.96
= 100Ω. Typical
691.20
MAX
829.44
967.68
Cycles
Cycles
Cycles
Cycles
UNITS
Clock
Clock
Clock
Clock
ps
ps
ps
1105.92
7