MAX1028 Maxim Integrated Products, MAX1028 Datasheet - Page 8

• Manufacturer Part Number: MAX1028
• Description: (MAX1030 / MAX1028 / MAX1026) 10-Bit 300ksps ADCs with FIFO / Temp Sensor / Internal Reference
• Manufacturer: Maxim Integrated Products

10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
8
MAX1030
1, 17, 19,
2–12, 26,
27, 28
_______________________________________________________________________________________
QFN
25
13
14
15
16
18
20
21
22
23
24
—
—
—
—
—
—
MAX1030
QSOP
1–14
15
16
17
18
19
20
21
22
23
24
—
—
—
—
—
—
—
MAX1028
1–10
11
12
13
14
15
16
17
18
19
20
—
—
—
—
—
—
—
MAX1026
1–6
10
11
12
13
14
15
16
—
—
—
—
—
—
—
7
8
9
REF-/AIN14
REF-/AIN10
REF-/AIN6
AIN0–13
CNVST/
CNVST/
CNVST/
AIN0–9
AIN0–5
NAME
AIN15
AIN11
DOUT
SCLK
REF+
AIN7
GND
EOC
N.C.
V
DIN
CS
DD
No Connection. Not internally connected.
Analog Inputs
Analog Inputs
Analog Inputs
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF capacitor.
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
Active-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to V
End of Conversion Output. Data is valid after EOC pulls low.
FUNCTION
Pin Description
DD
.