CDC1631F-E Micronas Intermetall GmbH, CDC1631F-E Datasheet - Page 17

• Manufacturer Part Number: CDC1631F-E
• Description: Automotive Controller Specification
• Manufacturer: Micronas Intermetall GmbH

ADVANCE INFORMATION
5. Core Logic
5.1. Control Register CR
The Control Register CR serves to configure the ways by
which certain system resources are accessed during opera-
tion. The main purpose is to obtain a variable system config-
uration during IC test.
Upon each HIGH transition on the RESETQ pin, internal
hardware reads data from the address location 00FFF3h and
stores it to the CR. The state of the TEST pin at that time
specifies which program storage source is accessed for this
read:
Table 5–1: Control byte source
The system will thus start up according to the configuration
defined in address location 00FFF3h, automatically copied to
register CR.
RESLNG
r/w1:
r/w0:
This bit specifies the length of the reset pulse which is output
at pin RESETQ following an internal reset. If pin TEST is 1
the first reset after power on is short. The following resets
are as programmed by RESLNG. If pin TEST is 0, all resets
are long.
TSTTOG
This bit is used for test purposes only. If TSTTOG is true in
IC active mode, pin TEST can toggle the multifunction pins
between Bus mode and normal mode.
Micronas
r/w RESLNG TSTTOG
TEST
0 or NC
1
CR
7
6
Reset Pulse Length
Pulse length is 4095/F
Pulse length is 16/F
TEST Pin Toggle (Table 5–2)
Control byte source
internal ROM
(standard for stand-alone operation)
external, via multifunction pins in Bus
mode (for test purposes only)
Control Register
x
5
Value of 00FFF3h
MFM TSTROM IROM
4
3
XTAL
XTAL
2
IRAM
1
ICPU
June 11, 2003; 6251-617-1AI
0
Res
MFM
Table 5–2: TSTTOG and MFM usage in mask ROM parts
TSTROM
IROM
Table 5–3: TSTROM and IROM usage in mask ROM parts
IRAM
r/w1:
r/w0:
ICPU
r/w1:
r/w0:
Table 5–4: Some commonly used settings for address
location 00FFF3h. A copy is automatically transferred to the
CR during RESET exit.
TSTTOG
0
1
x
TSTROM
1
0
x
Code
FFh
ABh
TEST
Pin
0
1
Multifunction Pin Mode
(Table 5–2)
TestROM (Table 5–3)
Internal ROM (Table 5–3)
Internal RAM
Enable internal RAM.
Disable internal RAM.
Internal CPU
Enable internal CPU.
Disable internal CPU.
IROM
1
0
MFM
0
0
1
Operation Mode
Stand-alone with internal ROM or Flash
External program storage connected to
multifunction pins in Bus Mode
selected program storage
internal ROM
internal TestROM
external via Multifunction pins
in Bus mode
TEST pin
x
0
1
x
CDC1631F-E
Multifunction
Pins
Bus mode
Bus mode
normal mode
normal mode
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