AD9433-105 Analog Devices, AD9433-105 Datasheet - Page 10

• Manufacturer Part Number: AD9433-105
• Description: 12-Bit, 105/125 MSPS Analog-to-digital if Sampling Converter
• Manufacturer: Analog Devices

Figure TBD. Transformer-Coupled Analog Input Circuit
In the highest frequency applications, two transformers
connected in series may be necessary to minimize even order
harmonic distortion. The first transformer will isolate and
convert the signal to a differential signal, but the grounded input
on the primary side will degrade amplitude balance on the
secondary winding. This imbalance is caused by capacitive
coupling between the windings. Since one input to the first
transformer is grounded, there is little or no capacitive coupling,
resulting in an amplitude mismatch at the first transformers
output. A second transformer will improve the amplitude
balance, and thus improve the harmonic distortion. A wideband
transformer, such as the ADT1-1WT from Mini Circuits, is
recommended for these applications, as the bandwidth through
the two transformers will be be reduced by the 2.
Figure TBD. Driving the Analog Input with 2 transformers
for improved even order harmonics
Driving the ADC single-ended will degrade performance,
particularly even order harmonics. For best dynamic
performance, impedances at AIN and AIN should match.
Special care was taken in the design of the analog input section
of the AD9433 to prevent damage and corruption of data when
the input is overdriven. When the nominal input range is set for
2.0V
differentially. When set for 1.0V
0.5V
SFDR Optimization
The SFDR MODE pin enables (SFDR MODE=1) a proprietary
circuit that may improve the spurious free dynamic range (SFDR)
performance of the AD9433. It is useful in applications where the
dynamic range of the system is limited by discrete spurious
frequency content caused by non-linearities in the ADC transfer
function.
Enabling this circuit will give the circuit a dynamic transfer
function, meaning that the voltage threshold between two adjacent
output codes may change from clock cycle to clock cycle. While
improving spurious frequency content, this dynamic aspect of the
PrD 12/19/2000 10:46 AM
Analog
Source
Signal
50
50
p-p
p-p
, each analog input will be 1 V p-p when driven
when driven differentially.
1:1
1 : 1
1:1
25 W
25
PRELIMINARY TECHNICAL DATA
p-p
, each analog input will be
25
25
0 . 1
0.1 F
A I N
A D 9 4 3 3
A I N
AIN
A D 9 4 3 3
AIN
- 10 -
transfer function may be inappropriate for some time domain
applications of the converter. Connecting the SFDR MODE pin to
ground will disable this function. The typical performance curves
section of the data sheet illustrates the improvement in the linearity
of the converter and it's effect on spurious free dynamic range.
Digital Outputs
The digital outputs are 3V (2.7 V to 3.3 V) TTL/CMOS-
compatible for lower power consumption. The output data
format is selectable through the data format select (DFS)
CMOS input. DFS=1 selects offset binary; DFS=0 selects two's
compliment coding.
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9433 (VREFOUT). In normal operation the internal
reference is used by strapping Pin 45 to Pin 46 and placing a 0.1
adjusted by varying the reference voltage applied to the
AD9433. No appreciable degradation in performance occurs
when the reference is adjusted 5%. The full-scale range of the
ADC tracks reference voltage changes linearly.
Timing
The AD9433 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay
(t
Timing Diagram). The length of the output data lines and
loads placed on them should be minimized to reduce
transients within the AD9433; these transients can detract
from the converter’s dynamic performance. The minimum
guaranteed conversion rate of the AD9433 is 1 MSPS. At
internal clock rates below 1 MSPS, dynamic performance may
degrade.
+2047
Code
Code
-2048
F decoupling capacitor at VREFIN. The input range can be
4095
2048
2047
PD
-1
0
0
) after the rising edge of the encode command (see
Table I. Two’s Complement Output Coding
Table TBD. Offset Binary Output Coding
Range=2Vp-p
Range=2Vp-p
AIN-AIN (V)
AIN-AIN (V)
-0.00049
-0.00049
-1.000
-1.000
1.000
1.000
0
0
(DFS=1, V
(DFS=0, V
Range=1Vp-p
Range=1Vp-p
AIN-AIN (V)
AIN-AIN (V)
REF
-0.000245
REF
-0.000245
-0.5000
-0.5000
0.500
0.500
=+2.5V)
=+2.5V)
0
0
AD9433
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
Digital
Output
Digital
Output