AD9389/PCB Analog Devices, AD9389/PCB Datasheet - Page 24

• Manufacturer Part Number: AD9389/PCB
• Description: 800 MHz High Performance Hdmi/dvi Transmitter
• Manufacturer: Analog Devices

AD9389
Hex
Address
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
Read/Write or
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Bits
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[4:0]
[7:0]
[7:0]
[7:6]
[5:0]
[7:4]
[3:0]
[7:2]
[1:0]
[7:0]
[7:0]
Default
Value
10000100
***11100
10111111
***00100
10101000
***11110
01110000
***00010
00011110
***00000
00000000
***00100
10101000
***01000
00010010
***11011
10101100
00000000
00******
**000000
0000****
****0000
000000**
******00
00000000
00000000
Register Name
CSC_A4_LSB
CSC_B1_MSB
CSC_B1_LSB
CSC_B2_MSB
CSC_B2_LSB
CSC_B3_MSB
CSC_B3_LSB
CSC_B4_MSB
CSC_B4_LSB
CDC_C1_MSB
CSC_C1_LSB
CSC_C2_MSB
CSC_C2_LSB
CSC_C3_MSB
CSC_C3_LSB
CSC_C4_MSB
CSC_C4_LSB
VFE_hs_pla_MSB
VFE_hs_pla_LSB
VFE_hs_dur_MSB
VFE_hs_dur_LSB
VFE_vs_pla_MSB
VFE_vs_pla_LSB
VFE_vs_dur_MSB
VFE_vs_dur_LSB
VFE_hsDelayIn_MSB
Rev. 0 | Page 24 of 48
Description
CSC coefficient for equation:
R
G
B
MSB of 0x21.
CSC coefficient for equation:
R
G
B
MSB of 0x23.
CSC coefficient for equation:
R
G
B
MSB of 0x25.
CSC coefficient for equation:
R
G
B
MSB of 0x27.
CSC coefficient for equation:
R
G
B
MSB of 0x29.
CSC coefficient for equation:
R
G
B
MSB of 0x2B.
CSC coefficient for equation:
R
G
B
MSB of 0x2D.
CSC coefficient for equation:
R
G
B
MSB of 0x2F.
CSC coefficient for equation:
R
G
B
Most significant 8 bits for HSYNC placement for ITU
656 HSYNC regeneration.
HSYNC placement lower 2 bits (see 0x30).
Most significant 6 bits for HSYNC duration.
HSYNC duration lower 4 bits (see 0x31).
Most significant 4 bits for VSYNC placement for ITU
656 VSYNC regeneration.
VSYNC placement lower 6 bits (see 0x32).
Most significant 2 bits for VSYNC duration.
VSYNC duration lower 8 bits (see 0x33).
Most significant 8 bits for HSYNC delay in for ITU 656
HSYNC regeneration.
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (a1 × R
= (c1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
= (b1 × R
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (a2 × G
) + (c2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
) + (b2 × G
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + (c3 × B
) + (c3 × B
) + (c3 × B
) + (c3 × B
) + (c3 × B
) + (c3 × B
) + (c3 × B
) + (a3 × B
) + (a3 × B
) + (a3 × B
) + (a3 × B
) + (a3 × B
) + (a3 × B
) + (c3 × B
) + (a3 × B
) + (c3 × B
) + (a3 × B
) + (a3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
) + (b3 × B
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
) + c4
IN
) + c4
) + c4
) + c4
) + c4
) + c4
) + c4
) + c4
) + c4
) + a4
) + a4
) + a4
) + a4
) + a4
) + a4
) + a4
) + a4
) + a4
) + b4
) + b4
) + b4
) + b4
) + b4
) + b4
) + b4
) + b4
) + b4