AD9218-40 Analog Devices, AD9218-40 Datasheet - Page 16

• Manufacturer Part Number: AD9218-40
• Manufacturer: Analog Devices

AD9218
APPLICATIONS
The wide analog bandwidth of the AD9218 makes it attractive
for a variety of high-performance receiver and encoder appli-
cations. Figure 14 shows the dual ADC in a typical low cost
I and Q demodulator implementation for cable, satellite, or
wireless LAN modem receivers. The excellent dynamic perfor-
mance of the ADC at higher analog input frequencies and
encode rates empowers users to employ direct IF sampling
techniques. IF sampling eliminates or simplifies analog mixer
and filter stages to reduce total system cost and power.
EVALUATION BOARD
The AD9218 evaluation board offers an easy way to test the
AD9218. It provides a means to drive the analog inputs single-
endedly or differentially. Differential drive can be tested through
a wideband RF transformer or a differential output operational
amplifier, the AD8138. The two encode clocks are accessible via
on-board SMB connectors J2, J7. These clocks are buffered
on board to provide the clocks for an on-board DAC and latches.
The digital outputs and output clocks are available at two 40-pin
connectors, P3 and P4. The board has several different modes
of operation, and is shipped in the following configuration:
• Differential Analog Input (RF Transformer Mode)
• Normal Operation Timing Mode
• Internal Voltage Reference
Power Connector
Power is supplied to the board via a detachable 12-pin power strip.
+5 V – Optional Supply for Operational Amplifier
–5 V – Optional Supply for Operational Amplifier
V
V
V
V
V
Analog Inputs
The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. SMB connectors J4 and J6 are
used for A
REF
REF
DL
DD
D
– Supply for ADC Analog
– Supply for Support Logic and DAC
A – Optional External Reference Input
B – Optional External Reference Input
– Supply for ADC Outputs
IF IN
IN
and B
VCO
90
IN
respectively. These signals each drive a
BPF
BPF
AD9218
ADC
ADC
VCO
Q
I
wideband RF transformer T1, T2, allowing the ADC performance
for differential inputs to be measured using a single-ended source.
In this mode resistors R35, R33, R39, and R32 should not be in
place. Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF
capacitor to an on-chip resistor divider that provides dc bias.
Single-ended performance can be measured by bypassing the
transformers using connectors SMB J5 (Channel A) and J1
(Channel B). In this mode, place a 0 Ω resistor at R35 and R33
(A Channel) and place R39 and R32 (B Channel). Note that the
inverting analog inputs are terminated on the board with 25 Ω
(optimized for differential operation). When driving the board
single-ended these resistors (R1, R3) can be changed to 50 Ω to
provide balanced inputs. The operational amplifier can be
used by connecting to J5 (Channel A) and J1 (Channel B).
The ac-coupling capacitors on the top level should be removed
from the board to use the operational amplifier. The compo-
nents to use the op amp should be placed on the bottom of the
board. See PCB Bill of Materials list for values.
Encode
The encode clock for Channel A uses SMB connector J7.
Channel B encode uses SMB connector J2. Each clock input is
terminated on the board with 50 Ω to ground. The input clocks
are fed directly to the ADC and to buffers U5, U6, which drive
the DAC and latches. The clock inputs are TTL-compatible.
Voltage Reference
The AD9218 has an internal 1.25 V voltage reference. An exter-
nal reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18–E1 and E17–E19). To use external references,
connect to V
and use jumpers E20–E18 and E19–E21.
Normal Operation Mode
In this mode both converters are clocked by the same encode
clock, latency is five clock cycles (see Timing Diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set with the jumpers labeled S1 and S2 (near the analog input).
Data Align Mode
In this mode channel B output is delayed an additional one-half
cycle. Signals S1 (Pin 8) and signal S2 (Pin 9) are both held
high. This is set with the jumpers labeled S1 and S2 (near the
analog input).
Data Format Select
Data Format Select sets the output data format and the gain of
the ADC. Setting DFS (Pin 4) low sets the output format to be
offset binary and gain of 1; setting DFS high sets the output to
be two’s complement and gain of 1. Removing the jumper for
DFS sets the output data format to offset binary and a gain of 2;
setting DFS to the middle selection sets the output data format
to two’s complement and a gain of 2.
REF
A and V
REF
B pins on the power connector P1