LM2326 National Semiconductor, LM2326 Datasheet - Page 15

• Manufacturer Part Number: LM2326
• Description: PLLatinum Low Power Frequency Synthesizer for RF Personal Communications
• Manufacturer: National Semiconductor

1.7 Application Information
1.7.1 DEVICE PROGRAMMING AFTER FIRST
APPLYING V
Three MICROWIRE programming methods can be used to
change the function latch, R counter latch, and N counter
latch contents with close phase alignment of R and N
counters to minimize lock up time after the cold power up.
1.7.2 INITIALIZATION SEQUENCE METHOD
Loading the function latch with [C1, C2] = [1, 1] immediately
followed by an R counter load, then an N counter load, effi-
ciently programs the MICROWIRE. Loading the function
latch with [C1, C2] = [1, 1] programs the same function latch
as a load with [C1, C2] = [0, 1] and additionally provides an
internal reset pulse described below. This program se-
quence insures that the counters are at load point when the
N counter data is latched in and the part will begin counting
in close phase alignment.
The following results from latching the MICROWIRE with an
F latch word, [C1, C2] = [1, 1]:
1.7.3 CE METHOD
Programming the function latch, R counter latch and N
counter latch while the part is being held in a powerdown
state by CE allows lowest possible power dissipation. After
the MICROWIRE contents have been programmed and the
part is enabled, the R and N counter contents will resume
counting in close phase alignment. Note that after CE transi-
tions from LOW to HIGH, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the part up and down by pin control
in order to check for channel activity. The MICROWIRE does
not need to be reprogrammed each time the part is enabled
and disabled as long as it has been programmed at least
once after V
• The function latch contents are loaded.
• An internal pulse resets the R, N, and timeout counters to
• Latching the first N counter data after the initialization
load state conditions and will TRI-STATE the charge
pump. If the function latch is programmed for the syn-
chronous powerdown case; CE = HIGH, F[2] = HIGH,
F[18] = HIGH, this internal pulse triggers powerdown.
Refer to Section 1.3.1 POWERDOWN OPERATION sec-
tion for a synchronous powerdown description. Note that
the prescaler bandgap reference and the oscillator input
buffer are unaffected by the internal reset pulse, allowing
close phase alignment when counting resumes.
word will activate the same internal reset pulse. Succes-
sive N counter data loads without an initialization load will
not trigger the internal reset pulse.
CC
CC
was applied.
15
1.7.4 COUNTER RESET METHOD
This MICROWIRE programming method consists of a func-
tion latch load, [C1, C2] = [0, 1], enabling the counter reset
bit, F[1]. The R and N counter latches are then loaded fol-
lowed by a final function latch load that disables the counter
reset. This provides the same close phase alignment as the
initialization sequence method with direct control over the in-
ternal reset. Note that counter reset holds the counters at
load point and will TRI-STATE the charge pump, but does
not trigger synchronous powerdown. The counter reset
method requires an extra function latch load compared to the
initialization sequence method.
1.7.5 DEVICE PROGRAMMING
When
LMX2326, first determine the frequencies and mode of op-
eration desired. Data register is programmed with a 21-bit
data stream shifted into the R counter, N counter, or the F
latch. The Functional Description section shows the bits for
the R counter, and the corresponding information for the N
counter. The FL
FUNCTION AND INITIALIZATION LATCHES section. Typi-
cal numbers for a GSM application example are given. In the
example, the RF output is locking at 950 MHz (f
200 kHz channel spacing (f
reference input is 10 MHz (f
is 32. An example of both methods of FastLock will be
shown.
The last two bits (control bits C1 and C2) of each bit stream
identify which counter or FL
example, to program the R counter, C1 and C2 will be 0,0.
Immediately proceeding these two bits is the N, R, or F bits
providing the divide ratios and FastLock mode information.
For example, to load the N counter, the last two bits C1 and
C2 must be 10.
Once the control bits have been determined, the frequency
information must be determined. To begin, determine the N
and R counter values as follows:
For this example R and N are determined as follows:
programming
C1
0
1
0
1
Control Bits
N = 950 MHz/200 kHz = 4750
R = 10 MHz/200 kHz = 50
o
programming information is given in the
N = f
R = f
C2
0
0
1
1
the
vco
osc
o
comparison
and
and
osc
/f
/f
mode will be programmed. For
comparison
comparison
LMX2306,
) and the prescaler value (P)
R Counter
N Counter
Function Latch
Initialization
DATA Location
). The crystal oscillator
LMX2316,
www.national.com
vco
) with a
and