OPB16450UART Xilinx Corp., OPB16450UART Datasheet - Page 13

• Manufacturer Part Number: OPB16450UART
• Description: Ds433 August 18, 2004 Product Specification
• Manufacturer: Xilinx Corp.

Raw UART Interface
UART without an OPB interface
The raw UART interface (the OPB UART without the OPB IPIF) is nearly identical to the interface described in the National
Semiconductor PC16550D UART with FIFOs data sheet (June, 1995), (http://www.national.com/pf/PC/PC16550D.html) with
the following major differences:
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Description of the raw interface signals
Sysclock. This is the primary UART reference clock. All UART operations and bus transactions are synchronized to this sig-
nal.
Xin. Xin is the reference for the UART baud rate generator circuit. Xin is a clock enable input. If Xin is tied high, the baud rate
reference will be Sysclock. Otherwise, Xin should be a single Sysclock period pulse high, with whatever duty cycle is
required by the application.
Rclk. This is the 16x reference for the receiver portion of the UART. It is a clock enable and should be a single Sysclock
period pulse high, with whatever duty cycle is required by the application. To simplify a system design Rclk may be tied to the
inverse of baudoutN.
Dout(7:0). UART read bus. Valid data will appear on this bus on the second Sysclock following Rd/RdN being brought active.
This bus is always driven.
Ddis. This signal goes low on the second Sysclock following Rd/RdN being brought active.
D(7:0). UART write bus.Valid data will be sampled during any clock period in which Wr/WrN are active with a valid address
and chip select applied.
AdsN. Address Strobe. This is a clock enable. Address pins (A2:A0) and Chip Select pins (Cs0, Cs1 and Cs2N) will be sam-
pled when AdsN is low and held when AdsN is high.
Wr/WrN. UART write pins. Data on D(7:0) is sampled during any Sysclock period in which Wr or WrN is active.
Rd/RdN. UART read pins. Data from the currently addressed register will appear on Dout(7:0) 2 Sysclock cycles following
Rd or RdN being asserted.
A(2:0). UART address bus. This address bus is a three bit address. The register map is identical to that described in the
National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995):
(http://www.national.com/pf/PC/PC16550D.html).
DS433 August 18, 2004
Product Specification
Sysclock. All bus transactions and UART operations are synchronized to this input clock.
Freeze. Asserting this signal disables interrupts and places the UART receiver and transmitter in the marking state.
Xin is a clock enable input, rather than a true clock.
Rclk is a clock enable input rather than a true clock.
Wr/WrN are clock enables.
Rd/RdN are clock enables.
AdsN is a clock enable.
Three state data bus (D) is separated into a read bus (Dout) and a write bus (D). Dout is always driven.
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