ADP3050-3.3 Analog Devices, ADP3050-3.3 Datasheet - Page 14

• Manufacturer Part Number: ADP3050-3.3
• Description: 200 Khz, 1 a Step-down High-voltage Switching Regulator
• Manufacturer: Analog Devices

ADP3050
To deal with this problem, the ADP3050 contains a backup
drive stage to get everything started. As the output voltage
increases, so will the boost voltage. When the boost voltage
reaches around 2.5 V, the switch drive will transition smoothly
from the backup driver to the boosted driver. If the boost voltage
should decrease below around 2.5 V (i.e., short circuit, overload
condition), the backup stage will again take over to provide
switch drive. The minimum input voltage needed for the ADP3050
to function correctly is about 3.6 V (this will ensure proper opera-
tion of the internal circuitry), but a small amount of headroom
is needed for all step-down regulators. The following formula
gives the approximate minimum input voltage needed for a
given system, where V
TPC 13 for the appropriate value of V
typical minimum input voltage needed for 3.3 V and 5 V systems.
THERMAL CONSIDERATIONS
Several factors contribute to IC power dissipation: ac and dc
switch losses, boost current, and quiescent current. The following
formulas can be used to calculate these losses to determine the
power dissipation of the IC. These formulas assume continuous
mode operation, but they provide a reasonable estimate for dis-
continuous mode systems (do not use these formulas to calculate
efficiency at light loads).
Switch loss:
Boost current loss:
Quiescent current loss:
where V
the switch frequency (200 kHz), t
overlap time (~50 ns), β
switch (~50), I
and I
For example: for a 5 V to 3.3 V system with I
For a total IC power dissipation of:
P
SW
BIAS
=



SAT
P
(
P
P
I
is the quiescent current drawn from V
50 10
Q
OUT
SW
BOOST
is ~0.6 V at I
=
×
=
(
Q
×
5 10



V
is the quiescent current drawn from V
P
×
0 8 0 6
=
−
Q
P
SAT
9
.
TOTAL
0 8
V
×
50
P
=
.
×
IN
BOOST
−
0 8 5 0 200 10
(
3
×
V
.
(MIN)
)
OUT
SW
SAT
×
V
IN
.
+
V
×
OUT
3 3
=
= 410
5 0
is the current gain of the NPN power
(
IN
×
.
×
3 3 4 10
is the switch saturation voltage (see
.
= 800 mA (taken from TPC 13), f
P
=
.
.
5 0
3 3
2
=
I
SW

 +

Q
.
.
I
β
V
=
× ×
×
OUT
)
SW

 +

OUT
mW
+
+
OV
35
(
t
(
P
OV
V
0 85
is the switch current/voltage
BOOST
mW
×
SAT
.
OUT
+
×
V
×
V
−
V
OUT
). TPC 11 also shows the
3
I
SAT
OUT
IN
)
×
3
=
)
+
I
2
=
18
BIAS
OUT
P
OUT
×
Q
357
V
mW
(~4 mA).
)
IN
= 800 mA:
mW
×
IN
f
SW
(~1 mA)
)
SW
(12)
(11)
(13)
(10)
(9)
is
The ADP3050 uses a thermally enhanced SO-8 package with a
package thermal resistance, θ
layer board (poor layout techniques will result in a higher thermal
resistance). This allows the ADP3050 to provide 1 A load currents
in an SO-8 package. The maximum die temperature, T
calculated using the thermal resistance and the maximum ambient
temperature:
For the previous example (5 V to 3.3 V at 800 mA system, SO-8
thermally enhanced package using good layout techniques) with
a worst-case ambient temperature of 70°C:
The maximum operating junction (die) temperature is 125°C, so
this system will operate within the safe limits of the ADP3050.
Check the die temperature at minimum and maximum supply
voltages to ensure proper operation under all conditions. The PC
board and its copper traces will provide sufficient heat-sinking,
but be sure to follow the layout suggestions in the Board Layout
Guidelines section. For any design that combines high output
current with high duty cycle and/or high input voltage, the junc-
tion temperature must be calculated to ensure normal operation.
Always use the equations in this section to estimate the power
dissipation.
BOARD LAYOUT GUIDELINES
A good board layout is essential when designing a switching
regulator. The high switching currents along with parasitic
wiring inductances can generate significant voltage transients and
cause havoc in sensitive circuits. For best results, keep the main
switching path as tight as possible (keep L1, D1, C
close together) and minimize the copper area of the SWITCH and
BOOST nodes (without violating current density requirements) to
reduce the amount of noise coupling into other sensitive nodes.
The external components should be located as close to the
ADP3050 as possible. For best thermal performance, use wide
copper traces for all IC connections, and always connect the
GND pin to a large piece of copper or ground plane. The ad-
ditional copper will improve heat transfer from the IC, greatly
reducing the package thermal resistance. Further improvements
of the thermal performance can be made by using multilayer
boards and using vias to transfer heat to the other layers. A
single layer board layout is shown in Figure 4. The amount of
copper used for the input, output, and ground traces can be
reduced, but were made large to improve the thermal perfor-
mance. For the 5 V and 3.3 V versions, leave out R1 and R2;
for the Adjustable version, remove the trace that shorts out R2.
Route all sensitive traces and components, such as those associated
with the feedback and compensation away from the BOOST and
SWITCH traces.
GND
V
IN
C
IN
T
IN
J
=
70
T
J
° +
C
ADP3050
=
T
GND
A
80
+
°
JA
C W
θ
, of around 80°C/W for a four-
J
/
A
SWITCH
×
×
P
0 41 103
TOTAL
.
D1
=
°
L1
C
C
OUT
IN
, and C
J
, can be
V
GND
OUT
(14)
OUT