AD9956 Analog Devices, AD9956 Datasheet - Page 8

• Manufacturer Part Number: AD9956
• Description: 2.7 GHz DDS-Based AgileRF
• Manufacturer: Analog Devices

AD9956
Parameter
TOTAL SYSTEM JITTER AND PHASE NOISE FOR
105.33 MHz ADC CLOCK GENERATION CIRCUIT
1
2
3
4
5
6
7
The input impedance of the REFCLK input is 1500 Ω. However, in order to provide matching on the clock line, an external 50 Ω load is used.
Driving the PLLREF input buffer, the crystal oscillator section of this input stage performs up to only 30 MHz.
The charge pump output compliance range is functionally 0.2 V to (CP_VDD − 0.2 V). The value listed here is the compliance range for 5% matching.
Measured as peak-to-peak from DRV to DRV .
For a 4.02 kΩ resistor from DRV_RSET to GND.
Assumes a 1 mA load.
I/O_UPDATE/PS<2:0> are detected by the AD9956 synchronous to the rising edge of SYNC_CLK. Each latency measurement is from the first SYNC_CLK rising edge
after the I/O_UPDATE/PS<2:0> state change.
Converter Limiting Jitter
Resultant SNR
Phase Noise of Fundamental
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ ≥1 MHz Offset
Min
Rev. 0 | Page 8 of 32
Typ
0.53
67
−75
−87
−93
−105
−145
−152
Max
ps rms
Unit
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
See the Loop Measurement Condi-
tions section