AD9923A Analog Devices, AD9923A Datasheet - Page 71

• Manufacturer Part Number: AD9923A
• Description: CCD Signal Processor
• Manufacturer: Analog Devices

Table 46. Miscellaneous Registers
Address
(Hex)
10
11
12
13
14
15
16
17
18
19
1A
Table 47. VD/HD Registers
Address
(Hex)
20
21
22
Data
Bits
[0]
[0]
[0]
[7:1]
[9:8]
[0]
[0]
[0]
[0]
[7:0]
[8]
[11:0]
[0]
[0]
Data
Bits
[0]
[0]
[12:0]
[24:13]
Default
Value
0
0
1
0
0
0
0
0
0
0
0
0
0
Default
Value
0
0
0
0
0
Update
Type
SCK
VD
SCK
SCK
SCK
SCK
SCK
SCK
VD
SCK
VD
Update
Type
SCK
SCK
VD
Name
SW_RST
OUTCONTROL
SYNCENABLE
TEST
OUTPUTPBLK
SYNCPOL
SYNCSUSPEND
TGCORE_RSTB
OSC_RST
TEST1
TEST2
UPDATE
PREVENTUP
GPO
Name
MASTER
VDHDPOL
HDRISE
VDRISE
Rev. 0 | Page 71 of 88
Description
Software reset. Bit resets to 0.
0: make all outputs dc inactive.
1: enable outputs at next VD edge.
0: configure Ball G7 as an output signal, determined by
Register 0x12, Bits[9:8].
1: external synchronization enable (configure Ball G7 as SYNC input).
Test mode only. Must be set to 0.
When SYNCENABLE = 0, selects which signal is output on the SYNC pin.
SYNC active polarity.
Suspends clocks during SYNC active pulse.
Timing core reset bar.
CLO oscillator reset.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Serial update line. Sets the HD line within the field to update the VD
updated registers.
Prevents the updating of the VD updated registers.
General-purpose output (GPO) value when SYNCENABLE = 0 and
OUTPUTPBLK = 2.
Description
VD/HD master or slave mode.
VD/HD active polarity.
Rising edge location for HD.
Rising edge location for VD.
1: reset Register 0x00 to Register 0x91 to default values.
0: CLPOB.
1: PBLK.
2: GPO (from Register 0x1A).
3: TESTOUT (from shutter registers).
0: active low.
1: active high.
0: don’t suspend.
1: suspend.
0: reset TG core.
1: resume operation.
0: oscillator in power-down state.
1: resume oscillator operation.
0: normal update.
1: prevent update of VD updated registers.
0: GPO is low at next VD edge.
1: GPO is high at next VD edge.
0: slave mode.
1: master mode.
0: low.
1: high.
AD9923A