AD9910 Analog Devices, AD9910 Datasheet - Page 8

• Manufacturer Part Number: AD9910
• Description: 3.3V CMOS Direct Digital Synthesizer
• Manufacturer: Analog Devices

PRELIMINARY TECHNICAL DATA
PIN DESCRIPTION & NOMENCLATURE
Pin #
1, 20, 72, 86,
87, 93, 97-
100
2
3, 6, 89, 92,
74-77, 83
17, 23, 30,
47, 57, 64
11, 15, 21,
28, 45, 56, 66
4, 5, 73, 78,
79, 82, 85,
88, 96
13, 16, 22,
29, 46, 58, 65
17, 23, 30,
47, 57, 64
7
8
9
10
12
14
18
19
24
25-27, 31-39,
42-44, 48
49, 50
40
41
51
52-54
55
59
60
NC
LOOP FILTER
AVDD(1.8V)
AVDD (3.3V)
DVDD (1.8V)
DVDD_I/O (3.3V)
AGND
DGND
DVDD
SYNC_I+
SYNC_I-
SYNC_O+
SYNC_O-
SYNC_SMP_ERR
MASTER_ RESET
EXT_PWR_DWN
PLL_LOCK
RAM_SWP_OVER
D<15:0>
F<1:0>
PDCLK
TxENABLE
NC
PROFILE <2:0>
IO_SYNC_CLK
I/O_UPDATE
OSK
Mnemonic
I
I
I
I
I
I
I
O
O
O
I
I
O
O
I
O
I
O
I/O
I
I
I
I
I
I
I
Description
Not Connected. Allow device pin to float.
PLL loop filter compensation pin. Attach a .01uF and a 243 ohm resistor from this pin to
AVDD to provide optimal PLL performance.
Analog Core VDD: 1.8V Analog Supply
Analog DAC VDD: 3.3V Analog Supply.
Digital Core VDD: 1.8V Digital Supply.
Digital Input/Output VDD: 3.3V Digital Supply.
Analog Ground.
Digital Ground.
Digital Core VDD: 1.8V Digital Supply
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
Digitaloutput (rising edge active). Synchronization signal from internal device sub-clocks
to synchronize external slave devices.
Digitaloutput (rising edge active). Synchronization signal from internal device sub-clocks
to synchronize external slave devices.
Digital output (active high). Sync sample error: A high on this pin indicates that the
AD9910 did not receive a valid sync signal on SYNC_I+/SYNC_I-.
Digital Input (active high). Master reset: clears all memory elements and sets registers to
default values.
Digital input (active high). External Power Down: A high level on this pin initates the
currently programmed power down mode. Please see the Power Down Modes section of
this document for further details. If unused, tie to ground.
Digital output (active high). PLL_Lock: A high indicates the clock multiplier PLL has
acquired lock to the reference clock input.
Digital output (active high). RAM Sweep Over: A high indicates the current RAM sweep
profile has completed.
Parallel input bus (active high).
Digital input to determine modulation format.
Digital output (clock) Parallel Data Clock provides a timing signal for aligning data at the
parallel inputs.
Digital input (active high). Transmit enable: In burst mode communications, a high on this
pin indicates new data for transmission. In continuous mode, this pin should be kept high.
No connection, but must be tied to DGND.
Digital inputs (active high). Profile select pins: used to select one of eight phase/frequency
profiles for the DDS. Changing the state of one of these pins will transfer the current
contents of all I/O buffers to the corresponding registers. State changes should be setup to
the IO_SYNC_CLK pin.
Digital output (clock). Output clock divided by four. Many of the digital inputs on the chip,
such as I/O_UPDATE and PROFILE<2:0> need to be setup to the rising edge of this signal
Digital input (active high). Input/Output update: A high on this pin transfers the contents
of the I/O buffers to the corresponding internal registers.
Digital input (active high). Output shaped keying: When the OSK features (manual or
Rev. PrD| Page 8 of 13
AD9910