AD9822 Analog Devices, AD9822 Datasheet - Page 2

• Manufacturer Part Number: AD9822
• Description: Complete 14-Bit CCD/CIS Signal Processor
• Manufacturer: Analog Devices

ANALOG SPECIFICATIONS
Parameter
MAXIMUM CONVERSION RATE
ACCURACY (Entire Signal Path)
ANALOG INPUTS
AMPLIFIERS
NOISE AND CROSSTALK
POWER SUPPLY REJECTION
DIFFERENTIAL VREF (@ 25 C)
TEMPERATURE RANGE
POWER SUPPLIES
OPERATING CURRENT
POWER DISSIPATION
AD9822–SPECIFICATIONS
3-Channel Mode with CDS
1-Channel Mode with CDS
ADC Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Offset Error
Gain Error
Input Signal Range
Allowable Reset Transient
Input Limits
Input Capacitance
Input Bias Current
PGA Gain at Minimum
PGA Gain at Maximum
PGA Gain Resolution
PGA Gain Monotonicity
Programmable Offset at Minimum
Programmable Offset at Maximum
Programmable Offset Resolution
Programmable Offset Monotonicity
Total Output Noise @ PGA Minimum
Total Output Noise @ PGA Maximum
Channel-Channel Crosstalk @ 6 MHz
AVDD = +5 V
CAPT–CAPB (2 V ADC Full-Scale Range)
Operating
Storage
AVDD
DRVDD
AVDD
DRVDD
Power-Down Mode Current
3-Channel Mode
1-Channel Mode
INL @ 6 MHz
DNL @ 6 MHz
No Missing Codes @ 6 MHz
3-Channel Mode @ 6 MHz
1-Channel Mode @ 6 MHz
2
0.25 V
1
2
1
(T
Gain = 1, unless otherwise noted.)
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
Min
15
12.5
–1.0
14
–240
–1.4
AVSS – 0.3
0.94
0
–65
4.75
3.0
–2–
Guaranteed
Guaranteed
Typ
14
–17.0/+3.5
–10.5/+1.5
–0.65/+0.75
–0.6/+0.65
14
–19
+3.5
2.0
1.0
10
10
1
5.7
64
–350
+350
512
1.5
6.0
<1
0.063
1.0
5.0
5.0
73
4
150
385
335
300
250
ADCCLK
= 15 MHz, f
Max
+1.1
+200
+6.9
AVDD + 0.3
0.9
1.06
+70
+150
5.25
5.25
450
410
CDSCLK1
= f
CDSCLK2
= 5 MHz, PGA
Unit
MSPS
MSPS
Bits
LSB
LSB
LSB
LSB
Bits
Bits
mV
% FSR
V p-p
V
V
pF
nA
V/V
V/V
Steps
mV
mV
Steps
LSB rms
LSB rms
LSB
% FSR
V
V
V
mA
mA
mW
mW
mW
mW
C
C
A
REV. A