AD9821 Analog Devices, AD9821 Datasheet - Page 8

• Manufacturer Part Number: AD9821
• Description: Complete 12-Bit 40 MSPS Imaging Signal Processor
• Manufacturer: Analog Devices

AD9821
IMAGER MODE AND AUX MODE TIMING
DATACLK
OUTPUT
OUTPUT
IMAGER
SIGNAL
DATA
CLPOB
VIN+
VIN–
PBLK
DATA
NOTES:
1. VIN+ AND VIN– SIGNALS ARE SAMPLED AT DATACLK RISING EDGES (CAN BE INVERTED USING THE CONTROL REGISTER).
2. INTERNAL SAMPLING DELAY (APERTURE)
3. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
NOTES:
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
EFFECTIVE PIXELS
EFFECTIVE PIXEL DATA
N–10
t
OD
N
t
ID
Figure 6. Typical Imager Mode Line Clamp Timing
N–9
OPTICAL BLACK PIXELS
t
ID
Figure 5. Imager Mode Timing
IS TYPICALLY 3 ns.
N+1
OB PIXEL DATA
t
H
t
CONV
N–8
–8–
N+2
HORIZONTAL
BLANKING
N+8
N–1
EFFECTIVE PIXELS
EFFECTIVE DATA
N+9
N
REV. 0