USB3250 Standard Microsystems Corporation, USB3250 Datasheet - Page 24

• Manufacturer Part Number: USB3250
• Description: Usb2.0 PHY IC
• Manufacturer: Standard Microsystems Corporation

Revision 1.5 (03-24-06)
7.2
Transceiver
Core
This block connects to either an external 12MHz crystal or an external clock source and generates a
480MHz multi-phase clock. The clock is used in the CRC block to over-sample the incoming received
data, resynchronize the transmit data, and is divided down to a 30MHz or 60MHz version (CLKOUT)
which acts as the system byte clock. The PLL block also outputs a clock valid signal to the other parts
of the transceiver when the clock signal is stable. All UTMI signals are synchronized to the CLKOUT
output. The behavior of the CLKOUT is as follows:
In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change
when the Macrocell is switched between HS to FS modes. In FS mode (8-bit mode) there are 5 CLK60
cycles per FS bit time, typically 40 CLK60 cycles per FS byte time. If a received byte contains a stuffed
bit then the byte boundary can be stretched to 45 CLK60 cycles, and two stuffed bits would result in
a 50 CLK60 cycles.
System Clocking
Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The
CLKOUT signal frequency error is less than 10% at this time.
The CLKOUT signal will fully meet the required accuracy of ±500ppm no later than 1.4ms after the
first transition of CLKOUT.
DATAOUT[1
DATAOUT[7:0
DATAOUT[7:0
DATAIN[15:8]
DATAIN[7:0]
TXVALI
RXVALID
TXVALID
D
5
H
H
]
]
Figure 7.1 Bidirectional 16-bit interface
:8]
DATASHEET
24
1=1
6
-bit mode, 0=8-bit mode
A
B
SELB
MU
X
SMSC GT3200, SMSC USB3250
DATABUS16_
TXVALID
DATA[15:8]
USB2.0 PHY IC
DATA[7:0]
8
VALID
H
Datasheet