AD9516-1 Analog Devices, AD9516-1 Datasheet - Page 63

• Manufacturer Part Number: AD9516-1
• Description: 14-Output Clock Generator
• Manufacturer: Analog Devices

Reg.
Addr
(Hex) Bit(s) Name
17
18
18
18
18
18
<1:0> Antibacklash <1>
<6:5> Lock Detect
<4>
<3>
<2:1> VCO Cal
<0>
Pulse Width 0
Counter
Digital Lock
Detect
Window
Disable
Digital
Lock Detect <3> = 1; disable lock detect.
Divider
VCO Cal
Now
Description
<7>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates
a locked condition.
<6>
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the
digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
<4> = 0; high range.
<4> = 1; low range.
Digital lock detect operation.
<3> = 0; normal lock detect operation.
VCO Calibration Divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
<2>
0
0
1
1
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence
to initiate a calibration is: program to a 0, followed by an update bit (Register 0x232<0>); then programmed to
1, followed by another update bit (Register 0x232<0>). This sequence gives complete control over when the
VCO calibration occurs relative to the programming of other registers that can impact the calibration.
<6> <5> <4>
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
<0>
0
1
0
1
<5>
0
1
0
1
<1> VCO Calibration Clock Divider
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
4
8
16 (default)
Antibacklash Pulse Width (ns)
2.9
1.3
6.0
2.9
PFD Cycles to Determine Lock
5
16
64
255
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
<3>
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
<2>
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 0 | Page 63 of 84
Level or
Dynamic
Signal
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
Status of VCO Frequency (active low).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).
Signal at STATUS Pin
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in
differential mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
(Status of REF1 frequency) AND (Status of REF2 frequency) .
(DLD) AND (Status of selected reference) AND (Status of VCO) .
Selected reference (Low = REF2, High = REF1).
AD9516-1