XRP7714 Exar, XRP7714 Datasheet - Page 18

• Manufacturer Part Number: XRP7714
• Description: Quad Channel Digital PWM Step Down Controller
• Manufacturer: Exar

S
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250µs steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
P
The XRP7714 allows the user to set the upper and lower bound for a power good signal per
channel.
SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB
resolution. When the output voltage is within bounds the power good signal is asserted high.
Typically the upper bound should be lower than the over-voltage threshold. In addition, the power
good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.
The power good delay is only set after the soft-start period is finished. If the channel has a pre-
charged condition that falls into the power good region, a power good flag is not set until the soft-
start is finished.
PWM S
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock
divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
© 2010 Exar Corporation
OFT
OWER
-S
TOP
WITCHING
G
OOD
The
F
LAG
SET_PWRG_TARG_MAX_CHx
F
REQUENCY
Enable
Signal
Vout
Ena ble
Signal
Vout
Q
Q
Fig. 24: Channel Soft-Stop Sequence
Fig. 23: Channel Power Up Sequence
u
u
a
a
d
d
Bit [15 :10]
DELAY
C
C
Bit [15:10]
DELAY
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h
a
a
18/27
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SS_RISE_CHx
REGISTER
PD_DELAY_CHx
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REGISTER
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FALL TIME
Bit [9:0]
RISE TIME
Bit [9:0]
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sets
P
P
W
W
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S
S
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D
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www.DataSheet4U.com
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X
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