S1A0903X01-Q0R0 Samsung Electronics, S1A0903X01-Q0R0 Datasheet - Page 22

• Manufacturer Part Number: S1A0903X01-Q0R0
• Description: AM/FM 1 Chip Tuner with PLL
• Manufacturer: Samsung Electronics

S1A0903X01
PROGRAMMABLE DIVIDER STRUCTURE
SERIAL INTERFACE
22
DO
A[1:0]
CE
CL
DI
0
1
2
3
CE
0
0
0
0
1
1
Mode
TEST
OUT
IN1
IN2
DOC1
A1
X
X
0
0
1
1
Data of IN1(TEST[1:0]=0) or IN2(TEST[1:0]=1,2,3) latched in DSR are
Data I[20:0] from DI pin are latched in IN1 or IN2 Data shift register on
When OS[1:0] in IN1 MODE is changed, N[16:0] is changed and R[3:0]
Data of OUT MODE latched in DSR are transferred on A point, which
IFCS bit is reset on B point, which makes Micro-processor restart IF
transferred to serial interface, which data are transferred to Micro-
processor through DO pin synchronized with the CL
B point.
is changed from PLL STOP MODE, Fr and Fc counter are reset which
make lock time of PLL fixed.
data transferred to Microprocessor through DO pin synchronized with
counter
A0
the CL.
A
DOC0
O20
I20
X
X
0
1
0
1
O19
I19
OUTMODE
Figure 5. Serial I/O Timing
X
X
X
X
0
1
O18
I18
Open
Open
When LOCK bit in OUT MODE is high, DO pin holds the
low state.
When IF counting is end, DO pin holds the low state.
Open
OUTMODE data are transferred through DO pin
O17
DI / DO
I17
O16
I16
DO Pin State
O3
I3
AM/FM 1CHIP TUNER WITH PLL
O2
I2
O1
I1
X : don't care
Remarks
O0
I0
B