HV9606 Supertex, Inc., HV9606 Datasheet - Page 6

• Manufacturer Part Number: HV9606
• Description: Switchmode PWM Controller
• Manufacturer: Supertex, Inc.

Functional Description,
R1 = 20MΩ – R2 – R3 = 20MΩ – 1.17MΩ – 3.5MΩ
R1 = 15.33MΩ
The programmable start/stop control circuit was designed to
provide this function. It inhibits the internal regulator, shuts down
the oscillator and holds the PWM reset until the programmed
start input voltage is exceeded. If the circuit is operating and the
effective input voltage drops below the programmed stop thresh-
old the internal regulator is inhibited, the oscillator is shut down
and the PWM is reset.
Start-Up Regulator
The start-up regulator guarantees a maximum V
current of 6µA at 20V at the Vin pin while it is inhibited by the
START/STOP circuit. When the effective input voltage exceeds
the programmed START voltage, the regulator is turned on and
seeks to provide a nominal 2.9V at the V
supply voltage for all internal circuitry within the HV9606 except
the start/stop circuit. This regulator is capable of input voltages
up to 250 Volts, which is the typical maximum arrester voltage
limit used to provide protection on telephone wires. Due to the
high voltage rating of the regulator the HV9606 can be used for
applications operating from rectified AC mains up to 140Vrms.
The regulator can supply a minimum of 5mA, which is sufficient
to power the internal circuitry and provide gate drive power for
the external MOSFET until the bootstrap circuit from the output
of the PWM drives the voltage on the V
regulator set point. This forces the regulator to turn off and
reduce the input current at the V
pin is typically bypassed with a capacitor of at least 1µF, which
provides the peak currents required by the voltage doubler and
in turn the gate driver for the external MOSFET.
For low power applications the circuit may be operated without
bootstrapping. Care should be taken to assure that the power
dissipation in the regulator does not become excessive, as it
might be if the input voltage is high and the gate drive energy
required is high (operating at high frequency).
It is also possible to use the HV9606 by powering V
voltages of 2.9V to 5.5V. In these applications the Vin pin should
be connected to SGND pin and the START and STOP pins may
be connected to SGND pin or left open. In this application the
START/STOP control and start-up regulator circuits are not
used.
V
To guarantee correct operation, internal circuitry is held reset by
an under voltage lockout (V
voltage is at least 100mV below the regulation set point. To
guarantee stable starting the V
100mV.
Oscillator
The oscillator circuit operates at twice the PWM output fre-
quency. The frequency can be programmed in the range of
30KHz to 800KHz by means of a single resistor connected from
the RT pin to SGND.
Synchronization
The SYNC pin is an input/output (I/O) port to a unique fault
tolerant peer-to-peer and/or to master clock synchronization
circuit. For synchronization the SYNC pins of multiple HV9606
based converters can be connected together and may also be
connected to the open drain/collector output of an external
DD
Under Voltage Lockout
DD
UVLO) until the regulator output
IN
DD
pin to leakage levels. The V
UVLO has a hysteresis of
DD
DD
pin higher than the
continued:
pin, which is the
IN
DD
pin leakage
from supply
DD
6
master clock. When connected in this manner the oscillators will
lock to the device with the highest operating frequency. The
LOW duty cycle of an external master clock should not exceed
50%. When synchronized in this manner, a permanent logic
HIGH or LOW condition on the SYNC pin will result in a loss of
synchronization, but the HV9606 based converters will continue
to operate at their individually set operating frequency. For this
reason the SYNC pin is considered fault tolerant, since loss of
synchronization will not result in total system failure.
Depending on the cumulative parasitic capacitance on the
SYNC pin when connected in the above manner a pull up resistor
may be required from the SYNC pin to the V
HV9606 based DC/DC converter circuit. The value of the
resistor will depend on the cumulative parasitic capacitance and
operating frequency.
Voltage Doubler
The HV9606 can operate on internal voltages ranging from 2.9V
to 5.5V. It may be difficult to find power MOSFETs capable of
operating with such low gate drive voltages. For this reason the
HV9606 incorporates a voltage doubler circuit that generates a
voltage on the VX2 pin that is approximate two times the V
voltage. This circuit uses capacitive charge transfer methods
and requires the connection of a capacitor (typically 0.01mF)
between the CA and CB pins as well as an energy storage
capacitor (typically 0.1mF) connected from the VX2 pin to PGND
pin. The voltage doubler operates at the PWM output frequency.
The gate driver output on the GATE pin operates from the VX2
voltage, logic level (5Volt) gate power MOSFETs may be used
when V
MOSFETs may be used when V
VX2 Under Voltage Lockout
To guarantee that sufficient gate drive voltage is available, an
under voltage lockout circuit (VX2 UVLO) monitors the VX2
voltage. If the VX2 voltage drops below 4.5V the gate driver
output of the PWM circuit is inhibited to prevent damage to the
power MOSFET. This under voltage lockout has a hysteresis of
400mV to prevent spurious operation.
Band Gap Reference
The operating limits of all internal circuits, except the START/
STOP circuit, are based on the 1% tolerance band gap reference
voltage available on the REF pin. It is capable of delivering
100mA for use by external circuitry without degrading the refer-
ence.
Current Sense and Current Limit
Current sensing is accomplished by means of a resistor con-
nected in series with the source of the external power MOSFET.
There are two independent comparators monitoring the voltage
drop across this resistor. One provides absolute peak current
limiting at 0.5VREF and the other provides peak current feed-
back to the PWM control loop.
Gate charge and capacitive loading reflected to the drain of the
power MOSFET results in high current spike at the positive
leading edge of gate drive when the MOSFET is turning on. This
can result in false tripping of the current limit comparator or false
operation of the control loop. To prevent this condition an 85nSec
leading edge current sense blanking circuit is incorporated in the
HV9606. This blanking period is sufficient in most applications to
achieve stable operation. However, additional filtering of the
MOSFET turn on current spike may be added by connecting a
resistor in series with the (CS) current sense pin and a capacitor
from the current sense pin to SGND pin.
DD
is bootstrapped at 3.3V or standard (10V) gate
DD
is bootstrapped at 5V.
DD
pin on each
HV9606
DD