L64733C LSI Logic Corporation, L64733C Datasheet - Page 17

• Manufacturer Part Number: L64733C
• Description: Tuner And Satellite Receiver Chipset Data Sheet 2/01
• Manufacturer: LSI Logic Corporation

Control Signals Interface
Analog-to-Digital Converter (ADC) Interface
The Control Signals Interface controls the operation of the L64734 and
is not associated with any particular interface.
IDDTN
RESET
XCTR_IN
XCTR[3]
XCTR[2:0]
The ADC module converts the incoming IVIN and QVIN signals into an
internal 6-bit digital representation for processing. The following pins
support the ADC module.
L64733C/L64734 Tuner and Satellite Receiver Chipset
Test
The IDDTN pin is an LSI Logic internal test pin. Tie the
IDDTN pin LOW for normal operation.
Reset
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the configuration registers.
Control Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN register bit.
Control Output/Sync Status Flag
The XCTR[3] signal indicates the synchronization status
for one of three synchronization modules in the L64734
or the XCTR[3] field in Group 4, APR 55. The three
modules are the Viterbi Decoder, Reed-Solomon
Deinterleaver (DI/RS), and Descrambler. For each of the
three synchronization outputs, the asserted XCTR[3]
signal indicates that synchronization is achieved for the
sync module chosen using the SSS[1:0] register bits.
When deasserted, the signal indicates an
out-of-synchronization condition.
Output Control
The XCTR[2:0] pins are external output control pins.
They are set by programming particular register bits.
XCTR[2] is mapped to CPG1 and XCTR[0] is multiplexed
with CPG2 when used with the L64733C Tuner IC. When
the on-chip serializer generates a serial 2- or 3-wire
protocol on the XCTR[2:0] pins, the mapping is XCTR[2]
= EN, XCTR[1] = SCL, and XCTR[0] = SDA.
Output
Output
Input
Input
Input
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